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[Qemu-devel] [PULL 01/19] hw/arm/virt: add DT property /secure-chosen/st
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/19] hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART |
Date: |
Tue, 16 Oct 2018 16:23:07 +0100 |
From: Jerome Forissier <address@hidden>
Bindings for /secure-chosen and /secure-chosen/stdout-path have been
proposed 1.5 years ago [1] and implemented in OP-TEE at the same time [2].
They've now been officially agreed on, so we can implement them
in QEMU.
This patch creates the property when the machine is secure.
[1] https://patchwork.kernel.org/patch/9602401/
[2] https://github.com/OP-TEE/optee_os/commit/4dc31c52544a
Signed-off-by: Jerome Forissier <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: commit message tweak]
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/virt.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 96dd4ef10c5..9f677825f9f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -712,6 +712,10 @@ static void create_uart(const VirtMachineState *vms,
qemu_irq *pic, int uart,
/* Mark as not usable by the normal world */
qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
+
+ qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
+ qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
+ nodename);
}
g_free(nodename);
--
2.19.0
- [Qemu-devel] [PULL 00/19] target-arm queue, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 07/19] net: cadence_gem: Announce availability of priority queues, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 08/19] net: cadence_gem: Use uint32_t for 32bit descriptor words, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 04/19] target/arm: Align cortex-r5 id_isar0, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 06/19] net: cadence_gem: Disable TSU feature bit, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 05/19] target/arm: Fix cortex-a7 id_isar0, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 03/19] target/arm: Define fields of ISAR registers, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 09/19] net: cadence_gem: Add macro with max number of descriptor words, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 02/19] target/arm: Fix aarch64_sve_change_el wrt EL0, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 10/19] net: cadence_gem: Add support for extended descriptors, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 01/19] hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART,
Peter Maydell <=
- [Qemu-devel] [PULL 11/19] net: cadence_gem: Add support for selecting the DMA MemoryRegion, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 12/19] net: cadence_gem: Implement support for 64bit descriptor addresses, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 19/19] coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 18/19] target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 17/19] target/arm: Mask PMOVSR writes based on supported counters, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 16/19] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 14/19] target-arm: powerctl: Enable HVC when starting CPUs to EL2, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 13/19] net: cadence_gem: Announce 64bit addressing support, Peter Maydell, 2018/10/16
- [Qemu-devel] [PULL 15/19] target/arm: Add the Cortex-A72, Peter Maydell, 2018/10/16