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[Qemu-devel] [PULL 01/10] hw/riscv/virt: Increase the number of interrup
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PULL 01/10] hw/riscv/virt: Increase the number of interrupts |
Date: |
Thu, 11 Oct 2018 20:31:41 +0000 |
Increase the number of interrupts to match the HiFive Unleashed board.
Signed-off-by: Alistair Francis <address@hidden>
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 91163d6cbf..7cb2742070 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -45,7 +45,7 @@ enum {
UART0_IRQ = 10,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
- VIRTIO_NDEV = 10
+ VIRTIO_NDEV = 0x35
};
enum {
--
2.17.1
- [Qemu-devel] [PULL 00/10] riscv-pullreq queue, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 01/10] hw/riscv/virt: Increase the number of interrupts,
Alistair Francis <=
- [Qemu-devel] [PULL 03/10] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 02/10] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 05/10] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 06/10] RISC-V: Allow setting and clearing multiple irqs, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 08/10] RISC-V: Update CSR and interrupt definitions, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 07/10] RISC-V: Move non-ops from op_helper to cpu_helper, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 04/10] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 09/10] RISC-V: Add missing free for plic_hart_config, Alistair Francis, 2018/10/11
- [Qemu-devel] [PULL 10/10] RISC-V: Don't add NULL bootargs to device-tree, Alistair Francis, 2018/10/11