[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 24/33] target/arm: Add some comments in Thumb decode
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 24/33] target/arm: Add some comments in Thumb decode |
Date: |
Mon, 8 Oct 2018 14:59:55 +0100 |
Add some comments to the Thumb decoder indicating what bits
of the instruction have been decoded at various points in
the code.
This is not an exhaustive set of comments; we're gradually
adding comments as we work with particular bits of the code.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/translate.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 25a8fe672f5..fcb33b8a503 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10623,6 +10623,10 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
tmp2 = load_reg(s, rm);
if ((insn & 0x70) != 0)
goto illegal_op;
+ /*
+ * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx:
+ * - MOV, MOVS (register-shifted register), flagsetting
+ */
op = (insn >> 21) & 3;
logic_cc = (insn & (1 << 20)) != 0;
gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
@@ -11674,7 +11678,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
rd = insn & 7;
op = (insn >> 11) & 3;
if (op == 3) {
- /* add/subtract */
+ /*
+ * 0b0001_1xxx_xxxx_xxxx
+ * - Add, subtract (three low registers)
+ * - Add, subtract (two low registers and immediate)
+ */
rn = (insn >> 3) & 7;
tmp = load_reg(s, rn);
if (insn & (1 << 10)) {
@@ -11711,7 +11719,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
}
break;
case 2: case 3:
- /* arithmetic large immediate */
+ /*
+ * 0b001x_xxxx_xxxx_xxxx
+ * - Add, subtract, compare, move (one low register and immediate)
+ */
op = (insn >> 11) & 3;
rd = (insn >> 8) & 0x7;
if (op == 0) { /* mov */
@@ -11848,7 +11859,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
break;
}
- /* data processing register */
+ /*
+ * 0b0100_00xx_xxxx_xxxx
+ * - Data-processing (two low registers)
+ */
rd = insn & 7;
rm = (insn >> 3) & 7;
op = (insn >> 6) & 0xf;
--
2.19.0
- [Qemu-devel] [PULL 10/33] target/arm: Clear unused predicate bits for LD1RQ, (continued)
- [Qemu-devel] [PULL 10/33] target/arm: Clear unused predicate bits for LD1RQ, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 09/33] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 23/33] target/arm: Add v8M stack checks on ADD/SUB/MOV of SP, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 08/33] target/arm: Handle SVE vector length changes in system mode, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 13/33] target/arm: Rewrite helper_sve_st[1234]*_r, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 32/33] target/arm: Add v8M stack checks for MSR to SP_NS, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 33/33] hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 31/33] target/arm: Add v8M stack checks for VLDM/VSTM, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 29/33] target/arm: Add v8M stack checks for T32 load/store single, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 30/33] target/arm: Add v8M stack checks for Thumb push/pop, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 24/33] target/arm: Add some comments in Thumb decode,
Peter Maydell <=
- [Qemu-devel] [PULL 25/33] target/arm: Add v8M stack checks on exception entry, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 28/33] target/arm: Add v8M stack checks for Thumb2 LDM/STM, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 27/33] target/arm: Add v8M stack checks for LDRD/STRD (imm), Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 26/33] target/arm: Add v8M stack limit checks on NS function calls, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 03/33] target/arm: Correct condition for v8M callee stack push, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 06/33] target/arm: Adjust sve_exception_el, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 05/33] target/arm: Define ID_AA64ZFR0_EL1, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 04/33] target/arm: Don't read r4 from v8M exception stackframe twice, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 07/33] target/arm: Pass in current_el to fp and sve_exception_el, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 02/33] virt: Suppress external aborts on virt-2.10 and earlier, Peter Maydell, 2018/10/08