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[Qemu-devel] [PATCH v3 06/15] target/arm: Clear unused predicate bits fo
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 06/15] target/arm: Clear unused predicate bits for LD1RQ |
Date: |
Fri, 5 Oct 2018 12:53:41 -0500 |
The 16-byte load only uses 16 predicate bits. But while
reusing the other load infrastructure, we find other bits
that are set and trigger an assert. To avoid this and
retain the assert, zero-extend the predicate that we pass
to the LD1 helper.
Tested-by: Laurent Desnogues <address@hidden>
Reported-by: Laurent Desnogues <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-sve.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 667879564f..4ee3bbca29 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4765,12 +4765,33 @@ static void do_ldrq(DisasContext *s, int zt, int pg,
TCGv_i64 addr, int msz)
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr t_pg;
TCGv_i32 desc;
+ int poff;
/* Load the first quadword using the normal predicated load helpers. */
desc = tcg_const_i32(simd_desc(16, 16, zt));
- t_pg = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
+ poff = pred_full_reg_offset(s, pg);
+ if (vsz > 16) {
+ /*
+ * Zero-extend the first 16 bits of the predicate into a temporary.
+ * This avoids triggering an assert making sure we don't have bits
+ * set within a predicate beyond VQ, but we have lowered VQ to 1
+ * for this load operation.
+ */
+ TCGv_i64 tmp = tcg_temp_new_i64();
+#ifdef HOST_WORDS_BIGENDIAN
+ poff += 6;
+#endif
+ tcg_gen_ld16u_i64(tmp, cpu_env, poff);
+
+ poff = offsetof(CPUARMState, vfp.preg_tmp);
+ tcg_gen_st_i64(tmp, cpu_env, poff);
+ tcg_temp_free_i64(tmp);
+ }
+
+ t_pg = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(t_pg, cpu_env, poff);
+
fns[msz](cpu_env, t_pg, addr, desc);
tcg_temp_free_ptr(t_pg);
--
2.17.1
- [Qemu-devel] [PATCH v3 00/15] target/arm: sve system mode patches, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 01/15] target/arm: Define ID_AA64ZFR0_EL1, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 02/15] target/arm: Adjust sve_exception_el, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 03/15] target/arm: Pass in current_el to fp and sve_exception_el, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 04/15] target/arm: Handle SVE vector length changes in system mode, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 05/15] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 08/15] target/arm: Rewrite helper_sve_ld[234]*_r, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 07/15] target/arm: Rewrite helper_sve_ld1*_r using pages, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 06/15] target/arm: Clear unused predicate bits for LD1RQ,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 09/15] target/arm: Rewrite helper_sve_st[1234]*_r, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 10/15] target/arm: Split contiguous loads for endianness, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 11/15] target/arm: Split contiguous stores for endianness, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 12/15] target/arm: Rewrite vector gather loads, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 13/15] target/arm: Rewrite vector gather stores, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 14/15] target/arm: Rewrite vector gather first-fault loads, Richard Henderson, 2018/10/05
- [Qemu-devel] [PATCH v3 15/15] target/arm: Pass TCGMemOpIdx to sve memory helpers, Richard Henderson, 2018/10/05
- Re: [Qemu-devel] [PATCH v3 00/15] target/arm: sve system mode patches, Peter Maydell, 2018/10/08