[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 7c0c09: target/s390x/cpu_model: Make check_co
|
From: |
Richard Henderson |
|
Subject: |
[Qemu-commits] [qemu/qemu] 7c0c09: target/s390x/cpu_model: Make check_compatibility()... |
|
Date: |
Tue, 30 Apr 2024 15:57:34 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 7c0c099a88fd45b3598118dd7dce9ba64a1d41b7
https://github.com/qemu/qemu/commit/7c0c099a88fd45b3598118dd7dce9ba64a1d41b7
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M target/s390x/cpu_models.c
Log Message:
-----------
target/s390x/cpu_model: Make check_compatibility() return boolean
As error.h suggested, the best practice for callee is to return
something to indicate success / failure.
With returned boolean, there's no need to check @err.
Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240425031232.1586401-2-zhao1.liu@intel.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 9c2df9c5e849ce2c24a6518a56e6e44371ff541e
https://github.com/qemu/qemu/commit/9c2df9c5e849ce2c24a6518a56e6e44371ff541e
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M target/s390x/cpu_models.c
Log Message:
-----------
target/s390x/cpu_model: Drop local @err in s390_realize_cpu_model()
Use @errp to fetch error information directly and drop the local
variable @err.
Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240425031232.1586401-3-zhao1.liu@intel.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 47ab3b21374627419cd400141cacd534b9281f7b
https://github.com/qemu/qemu/commit/47ab3b21374627419cd400141cacd534b9281f7b
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M target/s390x/cpu_models.c
M target/s390x/cpu_models.h
M target/s390x/kvm/kvm.c
Log Message:
-----------
target/s390x/cpu_models: Make kvm_s390_get_host_cpu_model() return boolean
As error.h suggested, the best practice for callee is to return
something to indicate success / failure.
So make kvm_s390_get_host_cpu_model() return boolean and check the
returned boolean in get_max_cpu_model() instead of accessing @err.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240425031232.1586401-5-zhao1.liu@intel.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: c6f1baf2d5a91fd2dcb31c3911fa5bec878faf6f
https://github.com/qemu/qemu/commit/c6f1baf2d5a91fd2dcb31c3911fa5bec878faf6f
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M target/s390x/cpu_models.c
Log Message:
-----------
target/s390x/cpu_models: Drop local @err in get_max_cpu_model()
Use @errp to fetch error information directly and drop the local
variable @err.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240425031232.1586401-6-zhao1.liu@intel.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 38098df346b3daaa8771f2aee64c6b47d4c00e56
https://github.com/qemu/qemu/commit/38098df346b3daaa8771f2aee64c6b47d4c00e56
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M target/s390x/cpu_models.h
M target/s390x/cpu_models_sysemu.c
M target/s390x/kvm/kvm.c
Log Message:
-----------
target/s390x/cpu_models: Make kvm_s390_apply_cpu_model() return boolean
As error.h suggested, the best practice for callee is to return
something to indicate success / failure.
So make kvm_s390_apply_cpu_model() return boolean and check the
returned boolean in apply_cpu_model() instead of accessing @err.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240425031232.1586401-7-zhao1.liu@intel.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 046bf2a6184f0a87b89b735ef77edd9a13a96656
https://github.com/qemu/qemu/commit/046bf2a6184f0a87b89b735ef77edd9a13a96656
Author: Zhao Liu <zhao1.liu@intel.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M target/s390x/cpu_models_sysemu.c
Log Message:
-----------
target/s390x/cpu_models_sysemu: Drop local @err in apply_cpu_model()
Use @errp to fetch error information directly and drop the local
variable @err.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240425031232.1586401-8-zhao1.liu@intel.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 69826741593644f6e9ee735cff37599c33764d67
https://github.com/qemu/qemu/commit/69826741593644f6e9ee735cff37599c33764d67
Author: Chris Friedt <chrisfriedt@gmail.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/misc/edu.c
Log Message:
-----------
hw: misc: edu: fix 2 off-by-one errors
In the case that size1 was zero, because of the explicit
'end1 > addr' check, the range check would fail and the error
message would read as shown below. The correct comparison
is 'end1 >= addr'.
EDU: DMA range 0x40000-0x3ffff out of bounds (0x40000-0x40fff)!
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1254
Signed-off-by: Chris Friedt <cfriedt@meta.com>
[thuth: Adjust patch with regards to the "end1 <= end2" check]
Message-ID: <20221018122551.94567-1-cfriedt@meta.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 3e64d7d7b8761107c39cc03da2d031d1d6f6912a
https://github.com/qemu/qemu/commit/3e64d7d7b8761107c39cc03da2d031d1d6f6912a
Author: Chris Friedt <chrisfriedt@gmail.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/misc/edu.c
Log Message:
-----------
hw: misc: edu: rename local vars in edu_check_range
This serves to make the local variables a bit less ambiguous.
The latter two arguments are named to match DMA_START, and
DMA_SIZE.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
Message-ID: <20221018122551.94567-2-cfriedt@meta.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 7b608e5d6c1d61430e81cd5c71b0277b99b03f3a
https://github.com/qemu/qemu/commit/7b608e5d6c1d61430e81cd5c71b0277b99b03f3a
Author: Chris Friedt <chrisfriedt@gmail.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/misc/edu.c
Log Message:
-----------
hw: misc: edu: use qemu_log_mask instead of hw_error
Log a guest error instead of a hardware error when
the guest tries to DMA to / from an invalid address.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
Message-ID: <20221018122551.94567-3-cfriedt@meta.com>
[thuth: Add missing #include statement, fix error reported by checkpatch.pl]
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 109f1a437f99d17059758d2e2ed8692d03744cbd
https://github.com/qemu/qemu/commit/109f1a437f99d17059758d2e2ed8692d03744cbd
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M stubs/meson.build
Log Message:
-----------
stubs: Add missing qga stubs
Compilation QGA without system and user fails
./configure --disable-system --disable-user --enable-guest-agent
Link failure:
/usr/bin/ld: libqemuutil.a.p/util_main-loop.c.o: in function
`os_host_main_loop_wait':
../util/main-loop.c:303: undefined reference to `replay_mutex_unlock'
/usr/bin/ld: ../util/main-loop.c:307: undefined reference to
`replay_mutex_lock'
/usr/bin/ld: libqemuutil.a.p/util_error-report.c.o: in function
`error_printf':
../util/error-report.c:38: undefined reference to `error_vprintf'
/usr/bin/ld: libqemuutil.a.p/util_error-report.c.o: in function
`vreport':
../util/error-report.c:225: undefined reference to `error_vprintf'
/usr/bin/ld: libqemuutil.a.p/util_qemu-timer.c.o: in function
`timerlist_run_timers':
../util/qemu-timer.c:562: undefined reference to `replay_checkpoint'
/usr/bin/ld: ../util/qemu-timer.c:530: undefined reference to
`replay_checkpoint'
/usr/bin/ld: ../util/qemu-timer.c:525: undefined reference to
`replay_checkpoint'
ninja: build stopped: subcommand failed.
Fixes: 3a15604900 ("stubs: include stubs only if needed")
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Message-ID: <20240426121347.18843-2-kkostiuk@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 26813f7f4acce1598ae7a52c2e79a86efe6177ee
https://github.com/qemu/qemu/commit/26813f7f4acce1598ae7a52c2e79a86efe6177ee
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M qga/meson.build
Log Message:
-----------
qga: Re-enable the qga-ssh-test when running without fuzzing
According to the comment in qga/meson.build, the test got disabled
since there were problems with the fuzzing job. But instead of
disabling this test completely, we should still be fine running
it when fuzzing is disabled.
Message-ID: <20240426162348.684143-1-thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: e40e129922a1114c05c846b094aa13496394613b
https://github.com/qemu/qemu/commit/e40e129922a1114c05c846b094aa13496394613b
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/char/stm32l4x5_usart.c
Log Message:
-----------
hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
"make check-qtest-aarch64" recently started failing on FreeBSD builds,
and valgrind on Linux also detected that there is something fishy with
the new stm32l4x5-usart: The code forgot to set the correct class_size
here, so the various class_init functions in this file wrote beyond
the allocated buffer when setting the subc->type field.
Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton")
Message-ID: <20240429075908.36302-1-thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 83561896ac9d1ffbc872293ff449b7df79c6c667
https://github.com/qemu/qemu/commit/83561896ac9d1ffbc872293ff449b7df79c6c667
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M scripts/ci/setup/build-environment.yml
Log Message:
-----------
build-environment: make some packages optional
Upgrading the s390x runner exposed some packages are not available for
it. Add an additional optional stage we only enable for arm64/x86_64
for now.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240426153938.1707723-2-alex.bennee@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 108d99742af1fa6e977dcfac9d4151b7915e33a3
https://github.com/qemu/qemu/commit/108d99742af1fa6e977dcfac9d4151b7915e33a3
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M .gitlab-ci.d/custom-runners.yml
R .gitlab-ci.d/custom-runners/ubuntu-20.04-s390x.yml
A .gitlab-ci.d/custom-runners/ubuntu-22.04-s390x.yml
Log Message:
-----------
gitlab: migrate the s390x custom machine to 22.04
20.04 is dead (from QEMU's point of view), long live 22.04!
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240426153938.1707723-3-alex.bennee@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 39ad72c2600af53d7697413afac382562910d3f8
https://github.com/qemu/qemu/commit/39ad72c2600af53d7697413afac382562910d3f8
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M .gitlab-ci.d/custom-runners/ubuntu-22.04-s390x.yml
Log Message:
-----------
gitlab: remove stale s390x-all-linux-static conf hacks
The libssh bug references 18.04 which we are no longer running. We
don't need to disable glusterfs because a linux-user build shouldn't
be trying to link to it anyway.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20240426153938.1707723-4-alex.bennee@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 8682ff696050584cfcb5bf43d567680ad339cf41
https://github.com/qemu/qemu/commit/8682ff696050584cfcb5bf43d567680ad339cf41
Author: Lev Kujawski <lkujaw@mailbox.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/ide/core.c
Log Message:
-----------
hw/ide/core.c (cmd_read_native_max): Avoid limited device parameters
Always use the native CHS device parameters for the ATA commands READ
NATIVE MAX ADDRESS and READ NATIVE MAX ADDRESS EXT, not those limited
by the ATA command INITIALIZE_DEVICE_PARAMETERS (introduced in patch
176e4961, hw/ide/core.c: Implement ATA INITIALIZE_DEVICE_PARAMETERS
command, 2022-07-07.)
As stated by the ATA/ATAPI specification, "[t]he native maximum is the
highest address accepted by the device in the factory default
condition." Therefore this patch substitutes the native values in
drive_heads and drive_sectors before calling ide_set_sector().
One consequence of the prior behavior was that setting zero sectors
per track could lead to an FPE within ide_set_sector(). Thanks to
Alexander Bulekov for reporting this issue.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1243
Signed-off-by: Lev Kujawski <lkujaw@mailbox.org>
Message-ID: <20221010085229.2431276-1-lkujaw@mailbox.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 622f8eb1586def9a374eca27878156dec69b8730
https://github.com/qemu/qemu/commit/622f8eb1586def9a374eca27878156dec69b8730
Author: Lev Kujawski <lkujaw@mailbox.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M tests/qtest/ide-test.c
Log Message:
-----------
tests/qtest/ide-test: Verify READ NATIVE MAX ADDRESS is not limited
Verify that the ATA command READ NATIVE MAX ADDRESS returns the last
valid CHS tuple for the native device rather than any limit
established by INITIALIZE DEVICE PARAMETERS.
Signed-off-by: Lev Kujawski <lkujaw@mailbox.org>
Message-ID: <20221010085229.2431276-2-lkujaw@mailbox.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: a88a04906b966ffdcda23a5a456abe10aa8c826e
https://github.com/qemu/qemu/commit/a88a04906b966ffdcda23a5a456abe10aa8c826e
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M .gitlab-ci.d/cirrus.yml
Log Message:
-----------
.gitlab-ci.d/cirrus.yml: Shorten the runtime of the macOS and FreeBSD jobs
Cirrus-CI introduced limitations to the free CI minutes. To avoid that
we are consuming them too fast, let's drop the usual targets that are
not that important since they are either a subset of another target
(like i386 or ppc being a subset of x86_64 or ppc64 respectively), or
since there is still a similar target with the opposite endianness
(like xtensa/xtensael, microblaze/microblazeel etc.).
Message-ID: <20240429100113.53357-1-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: cc6cb422e09592158586279fddeef107df05ecbb
https://github.com/qemu/qemu/commit/cc6cb422e09592158586279fddeef107df05ecbb
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M .gitlab-ci.d/cirrus.yml
R .gitlab-ci.d/cirrus/kvm-build.yml
Log Message:
-----------
.gitlab-ci.d/cirrus: Remove the netbsd and openbsd jobs
During the past months, the netbsd and openbsd jobs in the Cirrus-CI
were broken most of the time - the setup to run a BSD in KVM on Cirrus-CI
from gitlab via the cirrus-run script was very fragile, and since the
jobs were not run by default, it used to bitrot very fast.
Now Cirrus-CI also introduce a limit on the amount of free CI minutes
that you get there, so it is not appealing at all anymore to run
these BSDs in this setup - it's better to run the checks locally via
"make vm-build-openbsd" and "make vm-build-netbsd" instead. Thus let's
remove these CI jobs now.
Message-ID: <20240426113742.654748-1-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 845dd0385eb738690ee19e60111952a363bbf257
https://github.com/qemu/qemu/commit/845dd0385eb738690ee19e60111952a363bbf257
Author: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/core/clock.c
Log Message:
-----------
hw/core/clock: allow clock_propagate on child clocks
clock_propagate() has an assert that clk->source is NULL, i.e. that
you are calling it on a clock which has no source clock. This made
sense in the original design where the only way for a clock's
frequency to change if it had a source clock was when that source
clock changed. However, we subsequently added multiplier/divider
support, but didn't look at what that meant for propagation.
If a clock-management device changes the multiplier or divider value
on a clock, it needs to propagate that change down to child clocks,
even if the clock has a source clock set. So the assertion is now
incorrect.
Remove the assertion.
Signed-off-by: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
Message-id: 20240419162951.23558-1-raphael.poggi@lynxleap.co.uk
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Rewrote the commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a8aa8af99f87f20beca58f647a347ba576d59444
https://github.com/qemu/qemu/commit/a8aa8af99f87f20beca58f647a347ba576d59444
Author: Zenghui Yu <zenghui.yu@linux.dev>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M target/arm/hvf/hvf.c
Log Message:
-----------
hvf: arm: Remove PL1_WRITE_MASK
As it had never been used since the first commit a1477da3ddeb ("hvf: Add
Apple Silicon support").
Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev>
Message-id: 20240422092715.71973-1-zenghui.yu@linux.dev
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7b19a3554d2df22d29c75319a1dac17615d1b20e
https://github.com/qemu/qemu/commit/7b19a3554d2df22d29c75319a1dac17615d1b20e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M target/arm/tcg/hflags.c
Log Message:
-----------
target/arm: Restrict translation disabled alignment check to VMSA
For cpus using PMSA, when the MPU is disabled, the default memory
type is Normal, Non-cachable. This means that it should not
have alignment restrictions enforced.
Cc: qemu-stable@nongnu.org
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when
translation disabled")
Reported-by: Clément Chigot <chigot@adacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Clément Chigot <chigot@adacore.com>
Message-id: 20240422170722.117409-1-richard.henderson@linaro.org
[PMM: trivial comment, commit message tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bc980d66308d3eabf8718477083c5989ea71ad42
https://github.com/qemu/qemu/commit/bc980d66308d3eabf8718477083c5989ea71ad42
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M docs/system/arm/emulation.rst
Log Message:
-----------
docs/system/arm/emulation.rst: Add missing implemented features
As of version DDI0487K.a of the Arm ARM, some architectural features
which previously didn't have official names have been named. Add
these to the list of features which QEMU's TCG emulation supports.
Mostly these are features which we thought of as part of baseline 8.0
support. For SVE and SVE2, the names have been brought into line
with the FEAT_* naming convention of other extensions, and some
sub-components split into separate FEAT_ items. In a few cases (eg
FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240418152004.2106516-2-peter.maydell@linaro.org
Commit: e197395180511b093027c2bac3a34e6a84ddecdc
https://github.com/qemu/qemu/commit/e197395180511b093027c2bac3a34e6a84ddecdc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_CSV2_3 for -cpu max
FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose
information about whether branch targets and branch history trained
in one hardware described context can control speculative execution
in a different hardware context.
There is no branch prediction in TCG, so we don't need to do anything
to be compliant with this. Upadte the '-cpu max' ID registers to
advertise the feature.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-3-peter.maydell@linaro.org
Commit: 74360f3544be380f3a6f7a0f1cd8082ddd4a75ad
https://github.com/qemu/qemu/commit/74360f3544be380f3a6f7a0f1cd8082ddd4a75ad
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_ETS2 for -cpu max
FEAT_ETS2 is a tighter set of guarantees about memory ordering
involving translation table walks than the old FEAT_ETS; FEAT_ETS has
been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1
now gives no greater guarantees than ETS == 0.
FEAT_ETS2 requires:
* the virtual address of a load or store that appears in program
order after a DSB cannot be translated until after the DSB
completes (section B2.10.9)
* TLB maintenance operations that only affect translations without
execute permission are guaranteed complete after a DSB
(R_BLDZX)
* if a memory access RW2 is ordered-before memory access RW2,
then RW1 is also ordered-before any translation table walk
generated by RW2 that generates a Translation, Address size
or Access flag fault (R_NNFPF, I_CLGHP)
As with FEAT_ETS, QEMU is already compliant, because we do not
reorder translation table walk memory accesses relative to other
memory accesses, and we always guarantee to have finished TLB
maintenance as soon as the TLB op is done.
Update the documentation to list FEAT_ETS2 instead of the
no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org
Commit: f7ddd7b6a1f90cae677303e96b91e866a1570f6a
https://github.com/qemu/qemu/commit/f7ddd7b6a1f90cae677303e96b91e866a1570f6a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/kvm.c
Log Message:
-----------
target/arm: Implement ID_AA64MMFR3_EL1
Newer versions of the Arm ARM (e.g. rev K.a) now define fields for
ID_AA64MMFR3_EL1. Implement this register, so that we can set the
fields if we need to. There's no behaviour change here since we
don't currently set the register value to non-zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
Commit: 663163f00785805e61f524ef744914029b2b6a87
https://github.com/qemu/qemu/commit/663163f00785805e61f524ef744914029b2b6a87
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_Spec_FPACC for -cpu max
FEAT_Spec_FPACC is a feature describing speculative behaviour in the
event of a PAC authontication failure when FEAT_FPACCOMBINE is
implemented. FEAT_Spec_FPACC means that the speculative use of
pointers processed by a PAC Authentication is not materially
different in terms of the impact on cached microarchitectural state
(caches, TLBs, etc) between passing and failing of the PAC
Authentication.
QEMU doesn't do speculative execution, so we can advertise
this feature.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-6-peter.maydell@linaro.org
Commit: dcc5c018c7e6acddf81951bcbdf1019b9ab45f56
https://github.com/qemu/qemu/commit/dcc5c018c7e6acddf81951bcbdf1019b9ab45f56
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M tests/avocado/boot_linux_console.py
M tests/avocado/replay_kernel.py
Log Message:
-----------
tests/avocado: update sunxi kernel from armbian to 6.6.16
The Linux kernel 5.10.16 binary for sunxi has been removed from
apt.armbian.com. This means that the avocado tests for these machines
will be skipped (status CANCEL) if the old binary isn't present in
the avocado cache.
Update to 6.6.16, in the same way we did in commit e384db41d8661
when we moved to 5.10.16 in 2021.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2284
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20240415151845.1564201-1-peter.maydell@linaro.org
Commit: bd8e9ddf6f6915b8a67909a21e7f46f77a05767d
https://github.com/qemu/qemu/commit/bd8e9ddf6f6915b8a67909a21e7f46f77a05767d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M target/arm/cpu.c
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Refactor default generic timer frequency handling
The generic timer frequency is settable by board code via a QOM
property "cntfrq", but otherwise defaults to 62.5MHz. The way this
is done includes some complication resulting from how this was
originally a fixed value with no QOM property. Clean it up:
* always set cpu->gt_cntfrq_hz to some sensible value, whether
the CPU has the generic timer or not, and whether it's system
or user-only emulation
* this means we can always use gt_cntfrq_hz, and never need
the old GTIMER_SCALE define
* set the default value in exactly one place, in the realize fn
The aim here is to pave the way for handling the ARMv8.6 requirement
that the generic timer frequency is always 1GHz. We're going to do
that by having old CPU types keep their legacy-in-QEMU behaviour and
having the default for any new CPU types be a 1GHz rather han 62.5MHz
cntfrq, so we want the point where the default is decided to be in
one place, and in code, not in a DEFINE_PROP_UINT64() initializer.
This commit should have no behavioural changes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org
Commit: ee4336f9470b74f4dd3493d1fdbd61ff13005f9d
https://github.com/qemu/qemu/commit/ee4336f9470b74f4dd3493d1fdbd61ff13005f9d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
Currently QEMU CPUs always run with a generic timer counter frequency
of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz. For older versions of
the TF-A firmware that sbsa-ref runs, the frequency of the generic
timer is hardcoded into the firmware, and so if the CPU actually has
a different frequency then timers in the guest will be set
incorrectly.
The default frequency used by the 'max' CPU is about to change, so
make the sbsa-ref board force the CPU frequency to the value which
the firmware expects.
Newer versions of TF-A will read the frequency from the CPU's
CNTFRQ_EL0 register:
https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148
so in the longer term we could make this board use the 1GHz
frequency. We will need to make sure we update the binaries used
by our avocado test
Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
before we can do that.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org
Commit: 88c756bc9e5d38b6e46e631b9875ae954a319ed9
https://github.com/qemu/qemu/commit/88c756bc9e5d38b6e46e631b9875ae954a319ed9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/arm/sbsa-ref.c
M hw/watchdog/sbsa_gwdt.c
M include/hw/watchdog/sbsa_gwdt.h
Log Message:
-----------
hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
Currently the sbsa_gdwt watchdog device hardcodes its frequency at
62.5MHz. In real hardware, this watchdog is supposed to be driven
from the system counter, which also drives the CPU generic timers.
Newer CPU types (in particular from Armv8.6) should have a CPU
generic timer frequency of 1GHz, so we can't leave the watchdog
on the old QEMU default of 62.5GHz.
Make the frequency a QOM property so it can be set by the board,
and have our only board that uses this device set that frequency
to the same value it sets the CPU frequency.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
Commit: f037f5b4b91a32bf8f1ec2c8ff92d2d14242adb4
https://github.com/qemu/qemu/commit/f037f5b4b91a32bf8f1ec2c8ff92d2d14242adb4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/core/machine.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/internals.h
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
In previous versions of the Arm architecture, the frequency of the
generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
In Armv8.6, the architecture standardized this frequency to 1GHz.
Because there is no ID register feature field that indicates whether
a CPU is v8.6 or that it ought to have this counter frequency, we
implement this by changing our default CNTFRQ value for all CPUs,
with exceptions for backwards compatibility:
* CPU types which we already implement will retain the old
default value. None of these are v8.6 CPUs, so this is
architecturally OK.
* CPUs used in versioned machine types with a version of 9.0
or earlier will retain the old default value.
The upshot is that the only CPU type that changes is 'max'; but any
new type we add in future (whether v8.6 or not) will also get the new
1GHz default.
It remains the case that the machine model can override the default
value via the 'cntfrq' QOM property (regardless of the CPU type).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org
Commit: 4b00855f0ee2e2eee8fd2500ffef27c108be6dc3
https://github.com/qemu/qemu/commit/4b00855f0ee2e2eee8fd2500ffef27c108be6dc3
Author: Alexandra Diupina <adiupina@astralinux.ru>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/dma/xlnx_dpdma.c
Log Message:
-----------
hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
The DMA descriptor structures for this device have
a set of "address extension" fields which extend the 32
bit source addresses with an extra 16 bits to give a
48 bit address:
https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field
However, we misimplemented this address extension in several ways:
* we only extracted 12 bits of the extension fields, not 16
* we didn't shift the extension field up far enough
* we accidentally did the shift as 32-bit arithmetic, which
meant that we would have an overflow instead of setting
bits [47:32] of the resulting 64-bit address
Add a type cast and use extract64() instead of extract32()
to avoid integer overflow on addition. Fix bit fields
extraction according to documentation.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Cc: qemu-stable@nongnu.org
Fixes: d3c6369a96 ("introduce xlnx-dpdma")
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
Message-id: 20240428181131.23801-1-adiupina@astralinux.ru
[PMM: adjusted commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: afdc29b4a3a5a61c22342551bb38eea3731bfee1
https://github.com/qemu/qemu/commit/afdc29b4a3a5a61c22342551bb38eea3731bfee1
Author: Thomas Huth <thuth@redhat.com>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/char/stm32l4x5_usart.c
Log Message:
-----------
hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
"make check-qtest-aarch64" recently started failing on FreeBSD builds,
and valgrind on Linux also detected that there is something fishy with
the new stm32l4x5-usart: The code forgot to set the correct class_size
here, so the various class_init functions in this file wrote beyond
the allocated buffer when setting the subc->type field.
Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240429075908.36302-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: eb656a60fd93262b1e519b3162888bf261df7f68
https://github.com/qemu/qemu/commit/eb656a60fd93262b1e519b3162888bf261df7f68
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/arm/npcm7xx.c
Log Message:
-----------
hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
Use little endian for derivative OTP fuse key.
Cc: qemu-stable@nongnu.org
Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model")
Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240422125813.1403-1-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c771f883f2e6db3acd7cbed0fde273bfc6cc580e
https://github.com/qemu/qemu/commit/c771f883f2e6db3acd7cbed0fde273bfc6cc580e
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M docs/system/arm/b-l475e-iot01a.rst
M hw/display/Kconfig
A hw/display/dm163.c
M hw/display/meson.build
M hw/display/trace-events
A include/hw/display/dm163.h
Log Message:
-----------
hw/display : Add device DM163
This device implements the IM120417002 colors shield v1.1 for Arduino
(which relies on the DM163 8x3-channel led driving logic) and features
a simple display of an 8x8 RGB matrix. The columns of the matrix are
driven by the DM163 and the rows are driven externally.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-2-ines.varhol@telecom-paris.fr
[PMM: updated to new reset hold method prototype]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5b5b014b32458d68b69fe08e31e4d7b2c570836a
https://github.com/qemu/qemu/commit/5b5b014b32458d68b69fe08e31e4d7b2c570836a
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/arm/stm32l4x5_soc.c
M tests/qtest/stm32l4x5_gpio-test.c
M tests/qtest/stm32l4x5_syscfg-test.c
Log Message:
-----------
hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
to the optional DM163 display from the board code (GPIOs outputs need
to be connected to both SYSCFG inputs and DM163 inputs).
STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4c3308c61ee9adfbb0ad5764a6b0b232d325fb3c
https://github.com/qemu/qemu/commit/4c3308c61ee9adfbb0ad5764a6b0b232d325fb3c
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/arm/b-l475e-iot01a.c
Log Message:
-----------
hw/arm : Create Bl475eMachineState
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 49157207c0da4a0fea26464c6e57fa790009186b
https://github.com/qemu/qemu/commit/49157207c0da4a0fea26464c6e57fa790009186b
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M hw/arm/Kconfig
M hw/arm/b-l475e-iot01a.c
Log Message:
-----------
hw/arm : Connect DM163 to B-L475E-IOT01A
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a0c325c4b05cf7815739d6a84e567b95c8c5be7e
https://github.com/qemu/qemu/commit/a0c325c4b05cf7815739d6a84e567b95c8c5be7e
Author: Inès Varhol <ines.varhol@telecom-paris.fr>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
A tests/qtest/dm163-test.c
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest : Add testcase for DM163
`test_dm163_bank()`
Checks that the pin "sout" of the DM163 led driver outputs the values
received on pin "sin" with the expected latency (depending on the bank).
`test_dm163_gpio_connection()`
Check that changes to relevant STM32L4x5 GPIO pins are propagated to the
DM163 device.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-6-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b1e880789bc7dc07617e45e2d63d635cdbf2bf6d
https://github.com/qemu/qemu/commit/b1e880789bc7dc07617e45e2d63d635cdbf2bf6d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M .gitlab-ci.d/cirrus.yml
R .gitlab-ci.d/cirrus/kvm-build.yml
M .gitlab-ci.d/custom-runners.yml
R .gitlab-ci.d/custom-runners/ubuntu-20.04-s390x.yml
A .gitlab-ci.d/custom-runners/ubuntu-22.04-s390x.yml
M hw/char/stm32l4x5_usart.c
M hw/ide/core.c
M hw/misc/edu.c
M qga/meson.build
M scripts/ci/setup/build-environment.yml
M stubs/meson.build
M target/s390x/cpu_models.c
M target/s390x/cpu_models.h
M target/s390x/cpu_models_sysemu.c
M target/s390x/kvm/kvm.c
M tests/qtest/ide-test.c
Log Message:
-----------
Merge tag 'pull-request-2024-04-30' of https://gitlab.com/thuth/qemu into
staging
* Clean-ups for "errp" handling in s390x cpu_model code
* Fix a possible abort in the "edu" device
* Add missing qga stubs for stand-alone qga builds and re-enable qga-ssh-test
* Fix memory corruption caused by the stm32l4x5 uart device
* Update the s390x custom runner to Ubuntu 22.04
* Fix READ NATIVE MAX ADDRESS IDE commands to avoid a possible crash
* Shorten the runtime of Cirrus-CI jobs
# -----BEGIN PGP SIGNATURE-----
#
# iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmYwmaMRHHRodXRoQHJl
# ZGhhdC5jb20ACgkQLtnXdP5wLbUCERAAss5PJMG8rI4i4X/3nW49JYTlPOpgm/YX
# /UWF+eHUlqaqDdE0s+Pdw4Ozo3hXQt/E/CkcyflUTzVpnZtpv9vkhNWyjOoPV31v
# GQyQEzGvxZXl2S595XefyAyaMTP5maBhUTlyZWJo385cQraa60Ot5d4Mibr2CobY
# gIBRxEGB/frJYpbHJPxd/FxJV120gtuWAdZwGGYYYjwMzf2IKu2veODB8CnUErlX
# WNUsIzjtAslfh8Ek2ZmPzD7uktCUeigkukqIrLC1oEU3wzbJHkISv1kXCKPW/Nf6
# ISjVa5TqGwkiiF8fw9aYKvWrnPJS7JkhXw7Gz+b39d846kUdNyDfgLcYJeNS3cZ2
# R1xgR9B6hX8ZmikMbGC+0/Sv15u2Yr+bFxJBTJzq6zdOAb9EJNQY1hW2w/Lbrg3X
# LjY+ltcVweoSILT6AE6vGDPCHfBzO+6FcptFvw7ePvRGOlwAPZ3tEB9G2LEbCYgg
# BjWNP4aRuSfbUebO4x4Todz65WN8aY1EIBXORU/wgUlF2+zajWiOI5JRDKjWz2qQ
# gAMeCbLplli5bYrChWtouRIXtb061cQloULddu/SRFcaJOlV3SCzx4JfN15pU90s
# jRMIhMESAEj4NSfclhxsOiYp3ywZTvlQsVA6MgPlu2i3HJakQnt5zbg59TesRn2d
# r5PfAk83UnA=
# =0OB7
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 30 Apr 2024 12:11:31 AM PDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
* tag 'pull-request-2024-04-30' of https://gitlab.com/thuth/qemu:
.gitlab-ci.d/cirrus: Remove the netbsd and openbsd jobs
.gitlab-ci.d/cirrus.yml: Shorten the runtime of the macOS and FreeBSD jobs
tests/qtest/ide-test: Verify READ NATIVE MAX ADDRESS is not limited
hw/ide/core.c (cmd_read_native_max): Avoid limited device parameters
gitlab: remove stale s390x-all-linux-static conf hacks
gitlab: migrate the s390x custom machine to 22.04
build-environment: make some packages optional
hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
qga: Re-enable the qga-ssh-test when running without fuzzing
stubs: Add missing qga stubs
hw: misc: edu: use qemu_log_mask instead of hw_error
hw: misc: edu: rename local vars in edu_check_range
hw: misc: edu: fix 2 off-by-one errors
target/s390x/cpu_models_sysemu: Drop local @err in apply_cpu_model()
target/s390x/cpu_models: Make kvm_s390_apply_cpu_model() return boolean
target/s390x/cpu_models: Drop local @err in get_max_cpu_model()
target/s390x/cpu_models: Make kvm_s390_get_host_cpu_model() return boolean
target/s390x/cpu_model: Drop local @err in s390_realize_cpu_model()
target/s390x/cpu_model: Make check_compatibility() return boolean
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9c6c079bc6723da8061ccfb44361d67b1dd785dd
https://github.com/qemu/qemu/commit/9c6c079bc6723da8061ccfb44361d67b1dd785dd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-04-30 (Tue, 30 Apr 2024)
Changed paths:
M docs/system/arm/b-l475e-iot01a.rst
M docs/system/arm/emulation.rst
M hw/arm/Kconfig
M hw/arm/b-l475e-iot01a.c
M hw/arm/npcm7xx.c
M hw/arm/sbsa-ref.c
M hw/arm/stm32l4x5_soc.c
M hw/core/clock.c
M hw/core/machine.c
M hw/display/Kconfig
A hw/display/dm163.c
M hw/display/meson.build
M hw/display/trace-events
M hw/dma/xlnx_dpdma.c
M hw/watchdog/sbsa_gwdt.c
A include/hw/display/dm163.h
M include/hw/watchdog/sbsa_gwdt.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/internals.h
M target/arm/kvm.c
M target/arm/tcg/cpu32.c
M target/arm/tcg/cpu64.c
M target/arm/tcg/hflags.c
M tests/avocado/boot_linux_console.py
M tests/avocado/replay_kernel.py
A tests/qtest/dm163-test.c
M tests/qtest/meson.build
M tests/qtest/stm32l4x5_gpio-test.c
M tests/qtest/stm32l4x5_syscfg-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20240430' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/core/clock: allow clock_propagate on child clocks
* hvf: arm: Remove unused PL1_WRITE_MASK define
* target/arm: Restrict translation disabled alignment check to VMSA
* docs/system/arm/emulation.rst: Add missing implemented features
* target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
* tests/avocado: update sunxi kernel from armbian to 6.6.16
* target/arm: Make new CPUs default to 1GHz generic timer
* hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
* hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
* hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
* hw/arm: Add DM163 display to B-L475E-IOT01A board
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmYxILcZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pRzD/40UZrhNbS+FEANkXJ7qpUm
# giCKn8hVwteWY4T4LugUK9987lU0HZ7CGfsHoSaWNwa7RBdKUoDRqi/CQ1kCfeDO
# XET42do+6SJhak+4wmzEfYD+K7wnlauun0/dyqCjd2+JP0bln/MIY5r8JCN1GiYS
# YSAAKoZqAfG1bC3HmxELI9min09GPT+tzw0PAyVJipRtfE+ykZXoCytu0GWU5jB+
# VBI6SGmqMPd/c/7JfJV8KP8R0Mn3etA3hbOCx7YDL6cUmbepWtNPV8dLeTwofrpa
# 01uqN83PpbbSYr96QdXXa7Ov105hQH7e8jmr9+7jTpd3f9U7+GwsxxqDR1KDHLgn
# pUGZneoTDTkJugfXM28A0VoVB3eyJYPCLE9QQ/HXpChXc62NOQV5jcECgLiUDujH
# hVbeGEG0KViQlhMUfI3vIfTaIjEALDcNw5bxVUCqg8vdO6UtTXqqWdaS4Xgne8HB
# KeCu5xXngXEZjIgidZkmIC15FD60B19JdQz2WR+6BDCw8Ajm9iPWlj+ftZztuX/S
# cFSUZ05BPbTkBzAHG4GBvjXTdwsxX2acGBNtdETOQAxhkoRcug0Pn+BmrZQLqkm5
# mPKPW9FFxIkkgeK/ZdA4uIEwDZX/LQlnrX129XGt7DVr+yDNKekaVGfLL8x8alT1
# 3v0Ni/nntc6QtZDB88OIzA==
# =vAf/
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 30 Apr 2024 09:47:51 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
* tag 'pull-target-arm-20240430' of
https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits)
tests/qtest : Add testcase for DM163
hw/arm : Connect DM163 to B-L475E-IOT01A
hw/arm : Create Bl475eMachineState
hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
hw/display : Add device DM163
hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
target/arm: Refactor default generic timer frequency handling
tests/avocado: update sunxi kernel from armbian to 6.6.16
target/arm: Enable FEAT_Spec_FPACC for -cpu max
target/arm: Implement ID_AA64MMFR3_EL1
target/arm: Enable FEAT_ETS2 for -cpu max
target/arm: Enable FEAT_CSV2_3 for -cpu max
docs/system/arm/emulation.rst: Add missing implemented features
target/arm: Restrict translation disabled alignment check to VMSA
hvf: arm: Remove PL1_WRITE_MASK
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/de7e907d011c...9c6c079bc672
To unsubscribe from these emails, change your notification settings at
https://github.com/qemu/qemu/settings/notifications