[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 154c69: target/ppc: Fix nip on power manageme
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] 154c69: target/ppc: Fix nip on power management instructions |
|
Date: |
Thu, 28 Feb 2019 03:12:46 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 154c69f2b8512bdbfcd48a82bfd902e9449a895a
https://github.com/qemu/qemu/commit/154c69f2b8512bdbfcd48a82bfd902e9449a895a
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/excp_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Fix nip on power management instructions
Those instructions currently raise an exception from within
the helper. This tends to result in a bogus nip value in
the env context (typically the beginning of the TB). Such
a helper needs a gen_update_nip() first.
This fixes it with a different approach which is to throw the
exception from translate.c instead of the helper using
gen_exception_nip() which does the right thing. Exception
EXCP_HLT is also used instead of POWERPC_EXCP_STOP to effectively
exit from the CPU execution loop.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg : modified the commit log to comment the use of EXCP_HLT instead
of POWERPC_EXCP_STOP]
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3621e2c96082c6e5094dfec244077a135383d538
https://github.com/qemu/qemu/commit/3621e2c96082c6e5094dfec244077a135383d538
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Don't clobber MSR:EE on PM instructions
When issuing a power management instruction, we set MSR:EE
to force ppc_hw_interrupt() into calling powerpc_excp()
to deal with the fact that on P7 and P8, the system reset
caused by the wakeup needs to be generated regardless of
the MSR:EE value (using LPCR only).
This however means that the OS will see a bogus SRR1:EE
value which is a problem. It also prevents properly
implementing P9 STOP "light".
So fix this by instead putting some logic in ppc_hw_interrupt()
to decide whether to deliver or not by taking into account the
fact that we are waking up from sleep.
The LPCR isn't checked as this is done in the has_work() test.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 21c0d66a9c994c7a406f8a6d04a81c16332e0cb8
https://github.com/qemu/qemu/commit/21c0d66a9c994c7a406f8a6d04a81c16332e0cb8
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/translate.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Fix support for "STOP light" states on POWER9
STOP must act differently based on PSSCR:EC on POWER9. When set, it
acts like the P7/P8 power management instructions and wake up at 0x100
based on the wakeup conditions in LPCR.
When PSSCR:EC is clear however it will wakeup at the next instruction
after STOP (if EE is clear) or take the corresponding interrupts (if
EE is set).
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: dead760b00789d738f946f01849a2fdc57c5e765
https://github.com/qemu/qemu/commit/dead760b00789d738f946f01849a2fdc57c5e765
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Move "wakeup reset" code to a separate function
This moves the code to handle waking up from the 0x100 vector
from powerpc_excp() to a separate function, as the former is
already way too big as it is.
No functional change.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1e7fd61d97fd4b25c7c8f70eed6a3ffd50893b74
https://github.com/qemu/qemu/commit/1e7fd61d97fd4b25c7c8f70eed6a3ffd50893b74
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/ppc.c
M target/ppc/cpu.h
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Rename "in_pm_state" to "resume_as_sreset"
To better reflect what this does, as it's specific to some of the
P7/P8/P9 PM states, not generic.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a790e82b13854f443850cbf11b25cdb98f6885c5
https://github.com/qemu/qemu/commit/a790e82b13854f443850cbf11b25cdb98f6885c5
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/excp_helper.c
M target/ppc/translate.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Add POWER9 exception model
And use it to get the correct HILE bit in HID0
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f8154fd22bf80b1555bac46119747e899c09d0c9
https://github.com/qemu/qemu/commit/f8154fd22bf80b1555bac46119747e899c09d0c9
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Detect erroneous condition in interrupt delivery
It's very easy for the CPU specific has_work() implementation
and the logic in ppc_hw_interrupt() to be subtly out of sync.
This can occasionally allow a CPU to wakeup from a PM state
and resume executing past the PM instruction when it should
resume at the 0x100 vector.
This detects if it happens and aborts, making it a lot easier
to catch such bugs when testing rather than chasing obscure
guest misbehaviour.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d8ce5fd6643d5c568d6357354c205474e7022602
https://github.com/qemu/qemu/commit/d8ce5fd6643d5c568d6357354c205474e7022602
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Add Hypervisor Virtualization Interrupt on POWER9
This adds support for delivering that exception
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 67afe7759df4c3dec8abfc373b98d1a8d108ff66
https://github.com/qemu/qemu/commit/67afe7759df4c3dec8abfc373b98d1a8d108ff66
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/intc/xics.c
M hw/intc/xive.c
M hw/ppc/ppc.c
M include/hw/ppc/ppc.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Add POWER9 external interrupt model
Adds support for the Hypervisor directed interrupts in addition to the
OS ones.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: - modified the icp_realize() and xive_tctx_realize() to take
into account explicitely the POWER9 interrupt model
- introduced a specific power9_set_irq for POWER9 ]
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6eebe6dccb343f46ee2331e4173016b0feb0ab1d
https://github.com/qemu/qemu/commit/6eebe6dccb343f46ee2331e4173016b0feb0ab1d
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/excp_helper.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Add support for LPCR:HEIC on POWER9
This controls whether the External Interrupt (0x500) can be
delivered to the hypervisor or not.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 27461d69a0f108dea756419251acc3ea65198f1b
https://github.com/qemu/qemu/commit/27461d69a0f108dea756419251acc3ea65198f1b
Author: Prasad J Pandit <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
ppc: add host-serial and host-model machine attributes (CVE-2019-8934)
On ppc hosts, hypervisor shares following system attributes
- /proc/device-tree/system-id
- /proc/device-tree/model
with a guest. This could lead to information leakage and misuse.[*]
Add machine attributes to control such system information exposure
to a guest.
[*] https://wiki.openstack.org/wiki/OSSN/OSSN-0028
Reported-by: Daniel P. Berrangé <address@hidden>
Fix-suggested-by: Daniel P. Berrangé <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Daniel P. Berrangé <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d40bfcbbbb0ab2c9b585b94956d225ee51a013f8
https://github.com/qemu/qemu/commit/d40bfcbbbb0ab2c9b585b94956d225ee51a013f8
Author: David Hildenbrand <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M cpus.c
Log Message:
-----------
cpus: Properly release the iothread lock when killing a dummy VCPU
This enables CPU unplug under qtest.
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b8165118f52ce5ee88565d3cec83d30374efdc96
https://github.com/qemu/qemu/commit/b8165118f52ce5ee88565d3cec83d30374efdc96
Author: David Hildenbrand <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr_ovec.c
Log Message:
-----------
spapr: support memory unplug for qtest
Fake availability of OV5_HP_EVT, so we can test memory unplug in qtest.
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Acked-by: David Gibson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0d9d4872e54945c161933f1c1f6eddf1f18dfc90
https://github.com/qemu/qemu/commit/0d9d4872e54945c161933f1c1f6eddf1f18dfc90
Author: David Hildenbrand <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M tests/Makefile.include
A tests/device-plug-test.c
Log Message:
-----------
tests/device-plug: Add a simple PCI unplug request test
The issue with testing asynchronous unplug requests it that they usually
require a running guest to handle the request. However, to test if
unplug of PCI devices works, we can apply a nice little trick on some
architectures:
On system reset, x86 ACPI, s390x and spapr will perform the unplug,
resulting in the device of interest to get deleted and a DEVICE_DELETED
event getting sent.
On s390x, we still get a warning
qemu-system-s390x: -device virtio-mouse-pci,id=dev0:
warning: Plugging a PCI/zPCI device without the 'zpci' CPU feature
enabled; the guest will not be able to see/use this device
This will be fixed soon, when we enable the zpci CPU feature always
(Conny already has a patch for this queued).
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Collin Walling <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Acked-by: Cornelia Huck <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 613ebbec647d6d159a2fc81b4c34290765901de3
https://github.com/qemu/qemu/commit/613ebbec647d6d159a2fc81b4c34290765901de3
Author: David Hildenbrand <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M tests/device-plug-test.c
Log Message:
-----------
tests/device-plug: Add CCW unplug test for s390x
As CCW unplugs are surprise removals without asking the guest first,
we can test this without any guest interaction.
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Acked-by: Cornelia Huck <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c76480e5a0cc068b5fd39b50f4e36496bfaba95a
https://github.com/qemu/qemu/commit/c76480e5a0cc068b5fd39b50f4e36496bfaba95a
Author: David Hildenbrand <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M tests/device-plug-test.c
Log Message:
-----------
tests/device-plug: Add CPU core unplug request test for spapr
We can easily test this, just like PCI. On s390x, cpu unplug is not
supported. On x86 ACPI, cpu unplug requires guest interaction to work, so
it can't be tested that easily. We might add tests for ACPI later.
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 368807049344f437d467aea9af4bc8b05d5fbee2
https://github.com/qemu/qemu/commit/368807049344f437d467aea9af4bc8b05d5fbee2
Author: David Hildenbrand <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M tests/device-plug-test.c
Log Message:
-----------
tests/device-plug: Add memory unplug request test for spapr
We can easily test this, just like PCI. On x86 ACPI, we need guest
interaction to make it work, so it is not that easy to test. We might
add tests for that later on.
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 00fd075e1894fabff10dc7cd61af9130903a23c9
https://github.com/qemu/qemu/commit/00fd075e1894fabff10dc7cd61af9130903a23c9
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_rtas.c
M include/hw/ppc/spapr.h
M target/ppc/cpu.h
M target/ppc/mmu-hash64.c
Log Message:
-----------
target/ppc/spapr: Set LPCR:HR when using Radix mode
The HW relies on LPCR:HR along with the PATE to determine whether
to use Radix or Hash mode. In fact it uses LPCR:HR more commonly
than the PATE.
For us, it's also more efficient to do so, especially since unlike
the HW we do not maintain a cache of the current PATE and HV PATE
in a generic place.
Prepare the grounds for that by ensuring that LPCR:HR is set
properly on SPAPR machines.
Another option would have been to use a callback to get the PATE
but this gets messy when implementing bare metal support, it's
much simpler (and faster) to use LPCR.
Since existing migration streams may not have it, fix it up in
spapr_post_load() as well based on the pseudo-PATE entry that
we keep.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 38c784a1cce1a5fe68cf1a6474aad5a9f8c7dc1a
https://github.com/qemu/qemu/commit/38c784a1cce1a5fe68cf1a6474aad5a9f8c7dc1a
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/mmu-book3s-v3.c
M target/ppc/mmu-book3s-v3.h
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc/mmu: Use LPCR:HR to chose radix vs. hash translation
Now that LPCR:HR is set properly for SPAPR, use it for deciding
the translation type, which also works for bare metal
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2b9e0a6b9456dcb4b9e2f14d90a9db1622f462ba
https://github.com/qemu/qemu/commit/2b9e0a6b9456dcb4b9e2f14d90a9db1622f462ba
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/mmu-hash64.c
Log Message:
-----------
target/ppc: Re-enable RMLS on POWER9 for virtual hypervisors
Historically the 64-bit server MMU supports two way of configuring the
guest "real mode" mapping:
- The "RMA" with is a single chunk of physically contiguous
memory remapped as guest real, and controlled by the RMLS
field in the LPCR register and the RMOR register.
- The "VRMA" which uses special PTEs inserted in the partition
hash table by the hypervisor.
POWER9 deprecates the former, which is reflected by the filtering
done in ppc_store_lpcr() which effectively prevents setting of
the RMLS field.
However, when using fully emulated SPAPR machines, our qemu code
currently only knows how to define the guest real mode memory using
RMLS.
Thus you cannot run a SPAPR machine anymore with a POWER9 CPU
model today.
This works around it with a quirk in ppc_store_lpcr() to continue
allowing the RMLS field to be set when using a virtual hypervisor.
Ultimately we will want to implement configuring a VRMA instead
which will also be necessary if we want to migrate a SPAPR guest
between TCG and KVM but this is a lot more work.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2819282dae6c38b2c9d5499ad748b1471f26af1a
https://github.com/qemu/qemu/commit/2819282dae6c38b2c9d5499ad748b1471f26af1a
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/mmu-book3s-v3.h
Log Message:
-----------
target/ppc: Fix #include guard in mmu-book3s-v3.h
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3054b0ca4bdd83e0780bd76805ca17aa733031c8
https://github.com/qemu/qemu/commit/3054b0ca4bdd83e0780bd76805ca17aa733031c8
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash64.c
Log Message:
-----------
target/ppc: Fix ordering of hash MMU accesses
With mttcg, we can have MMU lookups happening at the same time
as the guest modifying the page tables.
Since the HPTEs of the hash table MMU contains two words (or
double worlds on 64-bit), we need to make sure we read them
in the right order, with the correct memory barrier.
Additionally, when using emulated SPAPR mode, the hypercalls
writing to the hash table must also perform the udpates in
the right order.
Note: This part is still not entirely correct
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 34525595fb379796241b0f3a9946bb21c4da1178
https://github.com/qemu/qemu/commit/34525595fb379796241b0f3a9946bb21c4da1178
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
Log Message:
-----------
target/ppc: Add basic support for "new format" HPTE as found on POWER9
POWER9 (arch v3) slightly changes the HPTE format. The B bits move
from the first to the second half of the HPTE, and the AVPN/ARPN
are slightly shorter.
However, under SPAPR, the hypercalls still take the old format
(and probably will for the foreseable future).
The simplest way to support this is thus to convert the HPTEs from
new to old format when reading them if the MMU model is v3 and there
is no virtual hypervisor, leaving the rest of the code unchanged.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
[dwg: Moved function to .c since there was no real need for it in the .h]
Signed-off-by: David Gibson <address@hidden>
Commit: 74c4912f097bab98a8b0f8ec2bee1db269505c14
https://github.com/qemu/qemu/commit/74c4912f097bab98a8b0f8ec2bee1db269505c14
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/helper_regs.h
Log Message:
-----------
target/ppc: Fix synchronization of mttcg with broadcast TLB flushes
Let's use the generic helper tlb_flush_all_cpus_synced() instead
of iterating the CPUs ourselves.
We do lose the optimization of clearing the "other" CPUs "need flush"
flags but this shouldn't be a problem in practice.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c4dae9cd37f5c6c7a6aa741f985f5abb57a6bb3f
https://github.com/qemu/qemu/commit/c4dae9cd37f5c6c7a6aa741f985f5abb57a6bb3f
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/helper.h
M target/ppc/misc_helper.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Flush the TLB locally when the LPIDR is written
Our TCG TLB only tags whether it's a HV vs a guest access, so it must
be flushed when the LPIDR is changed.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 79825f4d583a327c347db504f44bbb7470b130e8
https://github.com/qemu/qemu/commit/79825f4d583a327c347db504f44bbb7470b130e8
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M target/ppc/cpu.h
M target/ppc/mmu-book3s-v3.h
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
Log Message:
-----------
target/ppc: Rename PATB/PATBE -> PATE
That "b" means "base address" and thus shouldn't be in the name
of actual entries and related constants.
This patch keeps the synthetic patb_entry field of the spapr
virtual hypervisor unchanged until I figure out if that has
an impact on the migration stream.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3367c62f522bda6254b5760eab1ee94523a24ab2
https://github.com/qemu/qemu/commit/3367c62f522bda6254b5760eab1ee94523a24ab2
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/mmu-book3s-v3.c
M target/ppc/mmu-book3s-v3.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
Log Message:
-----------
target/ppc: Support for POWER9 native hash
(Might need more patch splitting)
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
[dwg: Hack to fix compile with some earlier include tweaks of mine]
Signed-off-by: David Gibson <address@hidden>
Commit: 539c6e735871aae54d9a61520efdfc02dc506d9b
https://github.com/qemu/qemu/commit/539c6e735871aae54d9a61520efdfc02dc506d9b
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc: Basic POWER9 bare-metal radix MMU support
No guest support yet
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d9c95c71aca38e3221ae38672494721650c99edc
https://github.com/qemu/qemu/commit/d9c95c71aca38e3221ae38672494721650c99edc
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr_drc.c
M include/hw/ppc/spapr_drc.h
Log Message:
-----------
spapr_drc: Allow FDT fragment to be added later
The current logic is to provide the FDT fragment when attaching a device
to a DRC. This works perfectly fine for our current hotplug support, but
soon we will add support for PHB hotplug which has some constraints, that
CPU, PCI and LMB devices don't seem to have.
The first constraint is that the "ibm,dma-window" property of the PHB
node requires the IOMMU to be configured, ie, spapr_tce_table_enable()
has been called, which happens during PHB reset. It is okay in the case
of hotplug since the device is reset before the hotplug handler is
called. On the contrary with coldplug, the hotplug handler is called
first and device is only reset during the initial system reset. Trying
to create the FDT fragment on the hotplug path in this case, would
result in somthing like this:
ibm,dma-window = < 0x80000000 0x00 0x00 0x00 0x00 >;
This will cause linux in the guest to panic, by simply removing and
re-adding the PHB using the drmgr command:
page = alloc_pages_node(nid, GFP_KERNEL, get_order(sz));
if (!page)
panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
The second and maybe more problematic constraint is that the
"interrupt-map" property needs to reference the interrupt controller
node using the very same phandle that SLOF has already exposed to the
guest. QEMU requires SLOF to call the private KVMPPC_H_UPDATE_DT hcall
at some point to know about this phandle. With the latest QEMU and SLOF,
this happens when SLOF gets quiesced. This means that if the PHB gets
hotplugged after CAS but before SLOF quiesce, then we're sure that the
phandle is not known when the hotplug handler is called.
The FDT is only needed when the guest first invokes RTAS to configure
the connector actually, long after SLOF quiesce. Let's postpone the
creation of FDT fragments for PHBs to rtas_ibm_configure_connector().
Since we only need this for PHBs, introduce a new method in the base
DRC class for that. DRC subtypes will be converted to use it in
subsequent patches.
Allow spapr_drc_attach() to be passed a NULL fdt argument if the method
is available. When all DRC subtypes have been converted, the fdt argument
will eventually disappear.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 62d38c9bd3a217fa21f4fe73526839eee5f2f770
https://github.com/qemu/qemu/commit/62d38c9bd3a217fa21f4fe73526839eee5f2f770
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_drc.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Generate FDT fragment for LMBs at configure connector time
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 345b12b99edefced1c103cc35bd3ae1373c9e9d6
https://github.com/qemu/qemu/commit/345b12b99edefced1c103cc35bd3ae1373c9e9d6
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_drc.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Generate FDT fragment for CPUs at configure connector time
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 46fd02990df10be2833c1c67b244aa87f0b61d6d
https://github.com/qemu/qemu/commit/46fd02990df10be2833c1c67b244aa87f0b61d6d
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr_drc.c
M hw/ppc/spapr_pci.c
M include/hw/pci-host/spapr.h
Log Message:
-----------
spapr/pci: Generate FDT fragment at configure connector time
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 09d876ce2c8ea3efd34e02d898c3122e04b814bc
https://github.com/qemu/qemu/commit/09d876ce2c8ea3efd34e02d898c3122e04b814bc
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_drc.c
M hw/ppc/spapr_pci.c
M include/hw/ppc/spapr_drc.h
Log Message:
-----------
spapr/drc: Drop spapr_drc_attach() fdt argument
All DRC subtypes have been converted to generate the FDT fragment at
configure connector time instead of attach time. The fdt and fdt_offset
arguments of spapr_drc_attach() aren't needed anymore. Drop them and
make the implementation of the dt_populate() method mandatory.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6cead90c5c9c462c56ddc41a0bd0b4cfef9f62a8
https://github.com/qemu/qemu/commit/6cead90c5c9c462c56ddc41a0bd0b4cfef9f62a8
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M include/hw/ppc/xics.h
Log Message:
-----------
xics: Write source state to KVM at claim time
The pseries machine only uses LSIs to support legacy PCI devices. Every
PHB claims 4 LSIs at realize time. When using in-kernel XICS (or upcoming
in-kernel XIVE), QEMU synchronizes the state of all irqs, including these
LSIs, later on at machine reset.
In order to support PHB hotplug, we need a way to tell KVM about the LSIs
that doesn't require a machine reset. An easy way to do that is to always
inform KVM when an interrupt is claimed, which really isn't a performance
path.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 743ed566c1d80991ab22fb404be706bb8b742335
https://github.com/qemu/qemu/commit/743ed566c1d80991ab22fb404be706bb8b742335
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics_spapr.h
Log Message:
-----------
spapr: Expose the name of the interrupt controller node
This will be needed by PHB hotplug in order to access the "phandle"
property of the interrupt controller node.
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ad62bff6383178fe95caff3ec63a6ca4ee398dec
https://github.com/qemu/qemu/commit/ad62bff6383178fe95caff3ec63a6ca4ee398dec
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr_irq: Expose the phandle of the interrupt controller
This will be used by PHB hotplug in order to create the "interrupt-map"
property of the PHB node.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ef28b98d58121b0a9ae94c9397d1def2531166ed
https://github.com/qemu/qemu/commit/ef28b98d58121b0a9ae94c9397d1def2531166ed
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr_pci.c
M include/hw/pci-host/spapr.h
Log Message:
-----------
spapr_pci: add PHB unrealize
To support PHB hotplug we need to clean up lingering references,
memory, child properties, etc. prior to the PHB object being
finalized. Generally this will be called as a result of calling
object_unparent() on the PHB object, which in turn would normally
be called as the result of an unplug() operation.
When the PHB is finalized, child objects will be unparented in
turn, and finalized if the PHB was the only reference holder. so
we don't bother to explicitly unparent child objects of the PHB,
with the notable exception of DRCs. This is needed to avoid a QEMU
crash when unplugging a PHB and resetting the machine before the
guest could handle the event. The DRCs are removed from the QOM tree
by pci_unregister_root_bus() and we must make sure we're not leaving
stale aliases under the global /dr-connector path.
The formula that gives the number of DMA windows is moved to an
inline function in the hw/pci-host/spapr.h header because it
will have other users.
The unrealize function is able to cope with partially realized PHBs.
It is hence used to implement proper rollback on the realize error
path.
Signed-off-by: Michael Roth <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 962b6c3650d6b43b21ffc12eb83e0ca39aace7af
https://github.com/qemu/qemu/commit/962b6c3650d6b43b21ffc12eb83e0ca39aace7af
Author: Michael Roth <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_drc.c
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_drc.h
Log Message:
-----------
spapr: create DR connectors for PHBs
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3998ccd092989da5b6abcd0b182f49a55c841e5f
https://github.com/qemu/qemu/commit/3998ccd092989da5b6abcd0b182f49a55c841e5f
Author: Nathan Fontenot <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: populate PHB DRC entries for root DT node
This add entries to the root OF node to advertise our PHBs as being
DR-capable in accordance with PAPR specification.
Signed-off-by: Nathan Fontenot <address@hidden>
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4b6d336f2c9e89350a8fafebb49422da24cbcb45
https://github.com/qemu/qemu/commit/4b6d336f2c9e89350a8fafebb49422da24cbcb45
Author: Michael Roth <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr_events.c
Log Message:
-----------
spapr_events: add support for phb hotplug events
Extend the existing EPOW event format we use for PCI
devices to emit PHB plug/unplug events.
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0a0a66cd1b79cba792cf00293a540e0330375f3c
https://github.com/qemu/qemu/commit/0a0a66cd1b79cba792cf00293a540e0330375f3c
Author: Michael Roth <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_pci.c
M include/hw/pci-host/spapr.h
Log Message:
-----------
spapr_pci: provide node start offset via spapr_populate_pci_dt()
PHB hotplug re-uses PHB device tree generation code and passes
it to a guest via RTAS. Doing this requires knowledge of where
exactly in the device tree the node describing the PHB begins.
Provide this via a new optional pointer that can be used to
store the PHB node's start offset.
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f130928d2a9b598ccdb61e1d834674f224eb9faa
https://github.com/qemu/qemu/commit/f130928d2a9b598ccdb61e1d834674f224eb9faa
Author: Michael Roth <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr_pci: add ibm, my-drc-index property for PHB hotplug
This is needed to denote a boot-time PHB as being hot-pluggable.
Signed-off-by: Michael Roth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: bb2bdd812ee9a9a38007b95c3967c528e552912c
https://github.com/qemu/qemu/commit/bb2bdd812ee9a9a38007b95c3967c528e552912c
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_drc.c
M hw/ppc/spapr_pci.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: add hotplug hooks for PHB hotplug
Hotplugging PHBs is a machine-level operation, but PHBs reside on the
main system bus, so we register spapr machine as the handler for the
main system bus.
Provide the usual pre-plug, plug and unplug-request handlers.
Move the checking of the PHB index to the pre-plug handler. It is okay
to do that and assert in the realize function because the pre-plug
handler is always called, even for the oldest machine types we support.
Signed-off-by: Michael Roth <address@hidden>
(Fixed interrupt controller phandle in "interrupt-map" and
TCE table size in "ibm,dma-window" FDT fragment, Greg Kurz)
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: dae5e39adae897e859685975afc1d2c0ade38505
https://github.com/qemu/qemu/commit/dae5e39adae897e859685975afc1d2c0ade38505
Author: Michael Roth <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: enable PHB hotplug for default pseries machine type
The 'dr_phb_enabled' field of that class can be set as part of
machine-specific init code. It will be used to conditionally
enable creation of DRC objects and device-tree description to
facilitate hotplug of PHBs.
Since we can't migrate this state to older machine types,
default the option to true and disable it for older machine
types.
Signed-off-by: Michael Roth <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9bcb5b29419c79f0249280aaed80d40d7d798eeb
https://github.com/qemu/qemu/commit/9bcb5b29419c79f0249280aaed80d40d7d798eeb
Author: Greg Kurz <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M tests/device-plug-test.c
Log Message:
-----------
tests/device-plug: Add PHB unplug request test for spapr
We can easily test this, just like PCI. PHB unplug is not supported
on s390x and x86 ACPI.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3dbe65c17890e4beefe9812590c723e17e611852
https://github.com/qemu/qemu/commit/3dbe65c17890e4beefe9812590c723e17e611852
Author: Cédric Le Goater <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: xive does not have a POWER7 interrupt model
Patch "target/ppc: Add POWER9 external interrupt model" should have
removed the section covering PPC_FLAGS_INPUT_POWER7.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f6d4dca807d853516fc307519f3260a432818bdc
https://github.com/qemu/qemu/commit/f6d4dca807d853516fc307519f3260a432818bdc
Author: Thomas Huth <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/ppc/pnv.c
M hw/ppc/pnv_psi.c
M hw/ppc/spapr.c
Log Message:
-----------
hw/ppc: Use object_initialize_child for correct reference counting
Both functions, object_initialize() and object_property_add_child() increase
the reference counter of the new object, so one of the references has to be
dropped afterwards to get the reference counting right. Otherwise the child
object will not be properly cleaned up when the parent gets destroyed.
Thus let's use now object_initialize_child() instead to get the reference
counting here right.
Suggested-by: Eduardo Habkost <address@hidden>
Signed-off-by: Thomas Huth <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b45b56baeecd6391bdfed5bd66f2cd59a3c86a77
https://github.com/qemu/qemu/commit/b45b56baeecd6391bdfed5bd66f2cd59a3c86a77
Author: Murilo Opsfelder Araujo <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: increase kernel size limit to 256MiB
Building kernel with CONFIG_DEBUG_INFO_REDUCED can generate a ~90MB image and
building with CONFIG_DEBUG_INFO can generate a ~225M one, both exceeds the
current limit of 32MiB.
Increasing kernel size limit to 256MiB should fit for now.
Signed-off-by: Murilo Opsfelder Araujo <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 584ea7e76f9aeb010188e23769566617d53877e3
https://github.com/qemu/qemu/commit/584ea7e76f9aeb010188e23769566617d53877e3
Author: Murilo Opsfelder Araujo <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: add INITRD_MAX_SIZE constant
The current 0x10000000 value is actually 256MiB, not 128MB as the comment
suggests. Move it to a constant and fix the comment (no change in the size
value).
Signed-off-by: Murilo Opsfelder Araujo <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b268a6162da8ef9daa6384f24d4b95a0385081eb
https://github.com/qemu/qemu/commit/b268a6162da8ef9daa6384f24d4b95a0385081eb
Author: Murilo Opsfelder Araujo <address@hidden>
Date: 2019-02-26 (Tue, 26 Feb 2019)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: use IEC binary prefixes to represent sizes
Using IEC binary prefixes from qemu/units.h provides a more human-friendly value
to size constants.
Suggested-by: Eric Blake <address@hidden>
Signed-off-by: Murilo Opsfelder Araujo <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1387294169a37e4694313e41e05fc32f211b0564
https://github.com/qemu/qemu/commit/1387294169a37e4694313e41e05fc32f211b0564
Author: Peter Maydell <address@hidden>
Date: 2019-02-28 (Thu, 28 Feb 2019)
Changed paths:
M cpus.c
M hw/intc/spapr_xive.c
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/intc/xive.c
M hw/ppc/pnv.c
M hw/ppc/pnv_psi.c
M hw/ppc/ppc.c
M hw/ppc/spapr.c
M hw/ppc/spapr_drc.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_irq.c
M hw/ppc/spapr_ovec.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_rtas.c
M include/hw/pci-host/spapr.h
M include/hw/ppc/ppc.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_drc.h
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics.h
M include/hw/ppc/xics_spapr.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.h
M target/ppc/misc_helper.c
M target/ppc/mmu-book3s-v3.c
M target/ppc/mmu-book3s-v3.h
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
M target/ppc/mmu_helper.c
M target/ppc/translate.c
M target/ppc/translate_init.inc.c
M tests/Makefile.include
A tests/device-plug-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190226' into
staging
ppc patch queue 2019-02-26
Next set of patches for ppc and spapr. There's a lot in this one:
* Support "STOP light" states on POWER9
* Add support for HVI interrupts on POWER9 (powernv machine)
* CVE-2019-8934: Don't leak host model and serial information to the guest
* Tests and cleanups for various hot unplug options
* Hash and radix MMU implementation on POWER9 for powernv machine
* PCI Host Bridge hotplug support for pseries machine
* Allow larger kernels and initrds for powernv machine
Plus a handful of miscellaneous fixes and cleanups.
The cpu hotplug tests and cleanups from David Hildenbrand aren't
solely power related. However the consensus amongst Michael Tsirkin,
David Hildenbrand, Cornelia Huck and myself was that it made most
sense to come in via my tree.
# gpg: Signature made Tue 26 Feb 2019 03:37:46 GMT
# gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg: aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-4.0-20190226: (50 commits)
ppc/pnv: use IEC binary prefixes to represent sizes
ppc/pnv: add INITRD_MAX_SIZE constant
ppc/pnv: increase kernel size limit to 256MiB
hw/ppc: Use object_initialize_child for correct reference counting
ppc/xive: xive does not have a POWER7 interrupt model
tests/device-plug: Add PHB unplug request test for spapr
spapr: enable PHB hotplug for default pseries machine type
spapr: add hotplug hooks for PHB hotplug
spapr_pci: add ibm, my-drc-index property for PHB hotplug
spapr_pci: provide node start offset via spapr_populate_pci_dt()
spapr_events: add support for phb hotplug events
spapr: populate PHB DRC entries for root DT node
spapr: create DR connectors for PHBs
spapr_pci: add PHB unrealize
spapr_irq: Expose the phandle of the interrupt controller
spapr: Expose the name of the interrupt controller node
xics: Write source state to KVM at claim time
spapr/drc: Drop spapr_drc_attach() fdt argument
spapr/pci: Generate FDT fragment at configure connector time
spapr: Generate FDT fragment for CPUs at configure connector time
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/adf2e451f357...1387294169a3
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] 154c69: target/ppc: Fix nip on power management instructions,
Peter Maydell <=