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[Qemu-commits] [qemu/qemu] 84b41e: target/hppa: use tb_cflags() to acces


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 84b41e: target/hppa: use tb_cflags() to access tb->cflags
Date: Thu, 07 Feb 2019 06:20:14 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 84b41e658b02a6738b47cc4e03176f1b81d9e1d1
      
https://github.com/qemu/qemu/commit/84b41e658b02a6738b47cc4e03176f1b81d9e1d1
  Author: Emilio G. Cota <address@hidden>
  Date:   2019-02-06 (Wed, 06 Feb 2019)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: use tb_cflags() to access tb->cflags

Signed-off-by: Emilio G. Cota <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 5c41496dd780fed67eadd64c59fc2cf21717ecf0
      
https://github.com/qemu/qemu/commit/5c41496dd780fed67eadd64c59fc2cf21717ecf0
  Author: Sven Schnelle <address@hidden>
  Date:   2019-02-06 (Wed, 06 Feb 2019)

  Changed paths:
    M target/hppa/gdbstub.c

  Log Message:
  -----------
  target/hppa: fix setting registers via gdb

While doing 'set $pcoqh=0xf0000000' i triggered the assertion below.
The argument order for deposit64() is wrong, and val needs to be
moved to the end.

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 68aa851aa21741ab0a3c019b641d6ce72f68b3d5
      
https://github.com/qemu/qemu/commit/68aa851aa21741ab0a3c019b641d6ce72f68b3d5
  Author: Sven Schnelle <address@hidden>
  Date:   2019-02-06 (Wed, 06 Feb 2019)

  Changed paths:
    M target/hppa/op_helper.c

  Log Message:
  -----------
  target/hppa: fix PSW Q bit behaviour to match hardware

PA-RISC specification says: "Setting the PSW Q-bit, PSW{28}, to 1
with this instruction, if it was not already 1, is an undefined
operation." However, at least HP-UX 10.20 sets the Q bit from 0 to 1
with the SSM instruction. Tested this both on HP9000/712 and
HP9000/785/C3750, both machines set the Q bit from 0 to 1 without
exception. This makes HP-UX 10.20 progress a little bit further.

Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
[rth: Add a comment to the code as well.]
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 1dca0549557caf962dc12dc0c225a98a6f2d5fa7
      
https://github.com/qemu/qemu/commit/1dca0549557caf962dc12dc0c225a98a6f2d5fa7
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-07 (Thu, 07 Feb 2019)

  Changed paths:
    M target/hppa/gdbstub.c
    M target/hppa/op_helper.c
    M target/hppa/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190206' into 
staging

Queued target/hppa patches

# gpg: Signature made Wed 06 Feb 2019 10:50:06 GMT
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <address@hidden>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-hppa-20190206:
  target/hppa: fix PSW Q bit behaviour to match hardware
  target/hppa: fix setting registers via gdb
  target/hppa: use tb_cflags() to access tb->cflags

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/713acc316ddc...1dca0549557c



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