[Qemu-commits] [qemu/qemu] 85ba72: RISC-V: Allow setting and clearing multiple irqs

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 85ba724fd6ad51360d61045476fd96d25dc15b9a
      
https://github.com/qemu/qemu/commit/85ba724fd6ad51360d61045476fd96d25dc15b9a
  Author: Michael Clark <address@hidden>
  Date:   2018-10-17 (Wed, 17 Oct 2018)

  Changed paths:
    M hw/riscv/sifive_clint.c
    M hw/riscv/sifive_plic.c
    M target/riscv/cpu.h
    M target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V: Allow setting and clearing multiple irqs

Change the API of riscv_set_local_interrupt to take a
write mask and value to allow setting and clearing of
multiple local interrupts atomically in a single call.
Rename the new function to riscv_cpu_update_mip.

Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: df354dd41064491342c2f1b5d4743eed40f0fa27
      
https://github.com/qemu/qemu/commit/df354dd41064491342c2f1b5d4743eed40f0fa27
  Author: Michael Clark <address@hidden>
  Date:   2018-10-17 (Wed, 17 Oct 2018)

  Changed paths:
    M target/riscv/Makefile.objs
    A target/riscv/cpu_helper.c
    R target/riscv/helper.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V: Move non-ops from op_helper to cpu_helper

This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.

Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 426f03482c8d2b98613f92a76bd034ac6bb0bc7a
      
https://github.com/qemu/qemu/commit/426f03482c8d2b98613f92a76bd034ac6bb0bc7a
  Author: Michael Clark <address@hidden>
  Date:   2018-10-17 (Wed, 17 Oct 2018)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_bits.h
    M target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V: Update CSR and interrupt definitions

* Add user-mode CSR defininitions.
* Reorder CSR definitions to match the specification.
* Change H mode interrupt comment to 'reserved'.
* Remove unused X_COP interrupt.
* Add user-mode interrupts.
* Remove erroneous until comments on machine mode interrupts.
* Move together paging mode and page table bit definitions.
* Move together interrupt and exception cause definitions.

Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: b6aa6cedf481b46beb7e49c85ab52fdbb3abcf8e
      
https://github.com/qemu/qemu/commit/b6aa6cedf481b46beb7e49c85ab52fdbb3abcf8e
  Author: Michael Clark <address@hidden>
  Date:   2018-10-17 (Wed, 17 Oct 2018)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  RISC-V: Add missing free for plic_hart_config

Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 7c28f4da20e5585dce7d575691dac5392b7c6f78
      
https://github.com/qemu/qemu/commit/7c28f4da20e5585dce7d575691dac5392b7c6f78
  Author: Michael Clark <address@hidden>
  Date:   2018-10-17 (Wed, 17 Oct 2018)

  Changed paths:
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  RISC-V: Don't add NULL bootargs to device-tree

Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 808ebd66e467f77c0d1f8c6346235f81e9c99cf2
      
https://github.com/qemu/qemu/commit/808ebd66e467f77c0d1f8c6346235f81e9c99cf2
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-25 (Thu, 25 Oct 2018)

  Changed paths:
    M hw/riscv/sifive_clint.c
    M hw/riscv/sifive_plic.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M target/riscv/Makefile.objs
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    A target/riscv/cpu_helper.c
    R target/riscv/helper.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' 
into staging

First RISC-V Patch Set for the 3.1 Soft Freeze

This pull request contains a handful of patches that have been floating
around various trees for a while but haven't made it upstream.  These
patches all appear quite safe.  They're all somewhat independent from
each other:

* One refactors our IRQ management function to allow multiple interrupts
  to be raised an once.  This patch has no functional difference.
* Cleaning up the op_helper/cpu_helper split.  This patch has no
  functional difference.
* Updates to various constants to keep them in sync with the latest ISA
  specification and to remove some non-standard bits that snuck in.
* A fix for a memory leak in the PLIC driver.
* A fix to our device tree handling to avoid provinging a NULL string.

I've given this my standard test: building the port, booting a Fedora
root filesytem on the latest Linux tag, and then shutting down that
image.  Essentially I'm just following the QEMU RISC-V wiki page's
instructions.  Everything looks fine here.

We have a lot more outstanding patches so I'll definately be submitting
another PR for the soft freeze.

# gpg: Signature made Wed 17 Oct 2018 21:17:52 BST
# gpg:                using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <address@hidden>"
# gpg:                 aka "Palmer Dabbelt <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/riscv/tags/riscv-for-master-3.1-sf0:
  RISC-V: Don't add NULL bootargs to device-tree
  RISC-V: Add missing free for plic_hart_config
  RISC-V: Update CSR and interrupt definitions
  RISC-V: Move non-ops from op_helper to cpu_helper
  RISC-V: Allow setting and clearing multiple irqs

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a4d710251fa5...808ebd66e467
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