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[RFC Patch 1/5] hw/display: Allwinner A10 HDMI controller emulation
|
From: |
Strahinja Jankovic |
|
Subject: |
[RFC Patch 1/5] hw/display: Allwinner A10 HDMI controller emulation |
|
Date: |
Tue, 5 Sep 2023 22:14:21 +0200 |
This patch adds basic Allwinner A10 HDMI controller support.
Emulated HDMI component will always show that a display is connected and
provide default EDID info.
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
---
hw/arm/allwinner-a10.c | 7 +
hw/display/allwinner-a10-hdmi.c | 214 ++++++++++++++++++++++++
hw/display/meson.build | 2 +
hw/display/trace-events | 4 +
include/hw/arm/allwinner-a10.h | 2 +
include/hw/display/allwinner-a10-hdmi.h | 69 ++++++++
6 files changed, 298 insertions(+)
create mode 100644 hw/display/allwinner-a10-hdmi.c
create mode 100644 include/hw/display/allwinner-a10-hdmi.h
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index b0ea3f7f66..2351d1a69b 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -41,6 +41,7 @@
#define AW_A10_WDT_BASE 0x01c20c90
#define AW_A10_RTC_BASE 0x01c20d00
#define AW_A10_I2C0_BASE 0x01c2ac00
+#define AW_A10_HDMI_BASE 0x01c16000
void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
{
@@ -95,6 +96,8 @@ static void aw_a10_init(Object *obj)
object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN4I);
object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
+
+ object_initialize_child(obj, "hdmi", &s->hdmi, TYPE_AW_A10_HDMI);
}
static void aw_a10_realize(DeviceState *dev, Error **errp)
@@ -210,6 +213,10 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
/* WDT */
sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, AW_A10_WDT_BASE, 1);
+
+ /* HDMI */
+ sysbus_realize(SYS_BUS_DEVICE(&s->hdmi), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->hdmi), 0, AW_A10_HDMI_BASE);
}
static void aw_a10_class_init(ObjectClass *oc, void *data)
diff --git a/hw/display/allwinner-a10-hdmi.c b/hw/display/allwinner-a10-hdmi.c
new file mode 100644
index 0000000000..0f046e3cc7
--- /dev/null
+++ b/hw/display/allwinner-a10-hdmi.c
@@ -0,0 +1,214 @@
+/*
+ * Allwinner A10 HDMI Module emulation
+ *
+ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "hw/qdev-properties.h"
+#include "qemu/module.h"
+#include "hw/display/allwinner-a10-hdmi.h"
+#include "trace.h"
+
+/* HDMI register offsets */
+enum {
+ REG_HPD = 0x000C, /* HDMI Hotplug detect */
+ REG_DDC_CTRL = 0x0500, /* DDC Control */
+ REG_DDC_SLAVE_ADDRESS = 0x0504, /* DDC Slave address */
+ REG_DDC_INT_STATUS = 0x050C, /* DDC Interrupt status */
+ REG_DDC_FIFO_CTRL = 0x0510, /* DDC FIFO Control */
+ REG_DDC_FIFO_ACCESS = 0x0518, /* DDC FIFO access */
+ REG_DDC_COMMAND = 0x0520, /* DDC Command */
+};
+
+/* HPD register fields */
+#define FIELD_HPD_HOTPLUG_DET_HIGH (1 << 0)
+
+/* DDC_CTRL register fields */
+#define FIELD_DDC_CTRL_SW_RST (1 << 0)
+#define FIELD_DDC_CTRL_ACCESS_CMD_START (1 << 30)
+
+/* FIFO_CTRL register fields */
+#define FIELD_FIFO_CTRL_ADDRESS_CLEAR (1 << 31)
+
+/* DDC_SLAVE_ADDRESS register fields */
+#define FIELD_DDC_SLAVE_ADDRESS_SEGMENT_SHIFT (24)
+#define FIELD_DDC_SLAVE_ADDRESS_OFFSET_SHIFT (8)
+
+/* DDC_INT_STATUS register fields */
+#define FIELD_DDC_INT_STATUS_TRANSFER_COMPLETE (1 << 0)
+
+/* DDC access command */
+enum {
+ DDC_COMMAND_E_DDC_READ = 6,
+};
+
+
+
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
+
+static uint64_t allwinner_a10_hdmi_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ AwA10HdmiState *s = AW_A10_HDMI(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+ uint32_t val = s->regs[idx];
+
+ switch (offset) {
+ case REG_HPD:
+ val = FIELD_HPD_HOTPLUG_DET_HIGH;
+ break;
+ case REG_DDC_FIFO_ACCESS:
+ val = s->edid_blob[s->edid_reg % sizeof(s->edid_blob)];
+ s->edid_reg++;
+ break;
+ case 0x544 ... AW_A10_HDMI_IOSIZE:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ default:
+ break;
+ }
+
+ trace_allwinner_a10_hdmi_read(offset, val);
+
+ return val;
+}
+
+static void allwinner_a10_hdmi_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwA10HdmiState *s = AW_A10_HDMI(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ switch (offset) {
+ case REG_DDC_CTRL:
+ if (val & FIELD_DDC_CTRL_SW_RST) {
+ val &= ~FIELD_DDC_CTRL_SW_RST;
+ }
+ if (val & FIELD_DDC_CTRL_ACCESS_CMD_START) {
+ val &= ~FIELD_DDC_CTRL_ACCESS_CMD_START;
+ if (s->regs[REG_INDEX(REG_DDC_COMMAND)] == DDC_COMMAND_E_DDC_READ)
{
+ uint32_t regval = s->regs[REG_INDEX(REG_DDC_SLAVE_ADDRESS)];
+ uint8_t segment = 0xFFu &
+ (regval >> FIELD_DDC_SLAVE_ADDRESS_SEGMENT_SHIFT);
+ uint8_t offset = 0xFFu &
+ (regval >> FIELD_DDC_SLAVE_ADDRESS_OFFSET_SHIFT);
+ if (segment == 0) {
+ s->edid_reg = offset;
+ }
+ }
+ }
+ break;
+ case REG_DDC_INT_STATUS:
+ /* Clear interrupts */
+ val = s->regs[REG_INDEX(REG_DDC_INT_STATUS)] & ~(val & 0xFFu);
+ /* Set transfer complete */
+ val |= FIELD_DDC_INT_STATUS_TRANSFER_COMPLETE;
+ break;
+ case REG_DDC_FIFO_CTRL:
+ if (val & FIELD_FIFO_CTRL_ADDRESS_CLEAR) {
+ val &= ~FIELD_FIFO_CTRL_ADDRESS_CLEAR;
+ }
+ break;
+ case 0x544 ... AW_A10_HDMI_IOSIZE:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ default:
+ break;
+ }
+
+ trace_allwinner_a10_hdmi_write(offset, (uint32_t)val);
+
+ s->regs[idx] = (uint32_t) val;
+}
+
+static const MemoryRegionOps allwinner_a10_hdmi_ops = {
+ .read = allwinner_a10_hdmi_read,
+ .write = allwinner_a10_hdmi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 1,
+};
+
+static void allwinner_a10_hdmi_reset_enter(Object *obj, ResetType type)
+{
+ AwA10HdmiState *s = AW_A10_HDMI(obj);
+
+ s->edid_reg = 0;
+}
+
+static void allwinner_a10_hdmi_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ AwA10HdmiState *s = AW_A10_HDMI(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_hdmi_ops, s,
+ TYPE_AW_A10_HDMI, AW_A10_HDMI_IOSIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+
+ qemu_edid_generate(s->edid_blob, sizeof(s->edid_blob), &s->edid_info);
+}
+
+static const VMStateDescription allwinner_a10_hdmi_vmstate = {
+ .name = "allwinner-a10-hdmi",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AwA10HdmiState, AW_A10_HDMI_REGS_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property allwinner_a10_hdmi_properties[] = {
+ DEFINE_EDID_PROPERTIES(AwA10HdmiState, edid_info),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void allwinner_a10_hdmi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+ device_class_set_props(dc, allwinner_a10_hdmi_properties);
+
+ rc->phases.enter = allwinner_a10_hdmi_reset_enter;
+ dc->vmsd = &allwinner_a10_hdmi_vmstate;
+}
+
+static const TypeInfo allwinner_a10_hdmi_info = {
+ .name = TYPE_AW_A10_HDMI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = allwinner_a10_hdmi_init,
+ .instance_size = sizeof(AwA10HdmiState),
+ .class_init = allwinner_a10_hdmi_class_init,
+};
+
+static void allwinner_a10_hdmi_register(void)
+{
+ type_register_static(&allwinner_a10_hdmi_info);
+}
+
+type_init(allwinner_a10_hdmi_register)
diff --git a/hw/display/meson.build b/hw/display/meson.build
index 413ba4ab24..0a36c3ed85 100644
--- a/hw/display/meson.build
+++ b/hw/display/meson.build
@@ -38,6 +38,8 @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true:
files('next-fb.c'))
system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c'))
+system_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true:
files('allwinner-a10-hdmi.c')
+
if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or
config_all_devices.has_key('CONFIG_VGA_PCI') or
config_all_devices.has_key('CONFIG_VMWARE_VGA') or
diff --git a/hw/display/trace-events b/hw/display/trace-events
index 2336a0ca15..8d0d33ce4d 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -177,3 +177,7 @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned
int size) "addr 0x%"PRI
macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32
macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32
macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting
mode to width %"PRId32 " height %"PRId32 " size %d"
+
+# allwinner-a10-hdmi.c
+allwinner_a10_hdmi_read(uint64_t offset, uint64_t data) "Read: offset 0x%"
PRIx64 " data 0x%" PRIx64
+allwinner_a10_hdmi_write(uint64_t offset, uint64_t data) "Write: offset 0x%"
PRIx64 " data 0x%" PRIx64
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index cd1465c613..db8cbeecfa 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -12,6 +12,7 @@
#include "hw/rtc/allwinner-rtc.h"
#include "hw/misc/allwinner-a10-ccm.h"
#include "hw/misc/allwinner-a10-dramc.h"
+#include "hw/display/allwinner-a10-hdmi.h"
#include "hw/i2c/allwinner-i2c.h"
#include "hw/watchdog/allwinner-wdt.h"
#include "sysemu/block-backend.h"
@@ -43,6 +44,7 @@ struct AwA10State {
AWI2CState i2c0;
AwRtcState rtc;
AwWdtState wdt;
+ AwA10HdmiState hdmi;
MemoryRegion sram_a;
EHCISysBusState ehci[AW_A10_NUM_USB];
OHCISysBusState ohci[AW_A10_NUM_USB];
diff --git a/include/hw/display/allwinner-a10-hdmi.h
b/include/hw/display/allwinner-a10-hdmi.h
new file mode 100644
index 0000000000..1065dca2f7
--- /dev/null
+++ b/include/hw/display/allwinner-a10-hdmi.h
@@ -0,0 +1,69 @@
+/*
+ * Allwinner A10 HDMI Module emulation
+ *
+ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_DISPLAY_ALLWINNER_A10_HDMI_H
+#define HW_DISPLAY_ALLWINNER_A10_HDMI_H
+
+#include "hw/display/edid.h"
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * @name Constants
+ * @{
+ */
+
+/** Size of register I/O address space used by HDMI device */
+#define AW_A10_HDMI_IOSIZE (0x1000)
+
+/** Total number of known registers */
+#define AW_A10_HDMI_REGS_NUM (AW_A10_HDMI_IOSIZE / sizeof(uint32_t))
+
+/** @} */
+
+/**
+ * @name Object model
+ * @{
+ */
+
+#define TYPE_AW_A10_HDMI "allwinner-a10-hdmi"
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10HdmiState, AW_A10_HDMI)
+
+/** @} */
+
+/**
+ * Allwinner A10 HDMI object instance state.
+ */
+struct AwA10HdmiState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ uint8_t edid_reg;
+ qemu_edid_info edid_info;
+ uint8_t edid_blob[128];
+
+ /** Array of hardware registers */
+ uint32_t regs[AW_A10_HDMI_REGS_NUM];
+};
+
+#endif /* HW_DISPLAY_ALLWINNER_A10_HDMI_H */
--
2.34.1