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[PATCH 1/5] target/arm: Disable FEAT_TRF in neoverse-v1
From: |
Richard Henderson |
Subject: |
[PATCH 1/5] target/arm: Disable FEAT_TRF in neoverse-v1 |
Date: |
Wed, 9 Aug 2023 19:35:44 -0700 |
Self-hosted trace is out of scope for QEMU.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/cpu64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 8019f00bc3..60e5f034d9 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -618,7 +618,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->dcz_blocksize = 4;
cpu->id_aa64afr0 = 0x00000000;
cpu->id_aa64afr1 = 0x00000000;
- cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
+ cpu->isar.id_aa64dfr0 = 0x000000f210305519ull; /* w/o FEAT_TRF */
cpu->isar.id_aa64dfr1 = 0x00000000;
cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */
cpu->isar.id_aa64isar1 = 0x0111000001211032ull;
@@ -628,7 +628,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */
cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x15011099;
+ cpu->isar.id_dfr0 = 0x05011099; /* w/o FEAT_TRF */
cpu->isar.id_isar0 = 0x02101110;
cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232042;
--
2.34.1
- Re: [PATCH 2/5] target/arm: Reduce dcz_blocksize to uint8_t, (continued)
[PATCH 4/5] target/arm: Support more GM blocksizes, Richard Henderson, 2023/08/09
[PATCH 1/5] target/arm: Disable FEAT_TRF in neoverse-v1,
Richard Henderson <=