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[PATCH 40/44] Add mailbox property tests. Part 1
|
From: |
Sergey Kambalin |
|
Subject: |
[PATCH 40/44] Add mailbox property tests. Part 1 |
|
Date: |
Wed, 26 Jul 2023 16:25:08 +0300 |
Signed-off-by: Sergey Kambalin <sergey.kambalin@auriga.com>
---
tests/qtest/bcm2838-mbox-property-test.c | 179 +++++++++++++++++++++++
tests/qtest/meson.build | 2 +-
2 files changed, 180 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/bcm2838-mbox-property-test.c
diff --git a/tests/qtest/bcm2838-mbox-property-test.c
b/tests/qtest/bcm2838-mbox-property-test.c
new file mode 100644
index 0000000000..ac173ed3ff
--- /dev/null
+++ b/tests/qtest/bcm2838-mbox-property-test.c
@@ -0,0 +1,179 @@
+/*
+ * Tests set for BCM2838 mailbox property interface.
+ *
+ * Copyright (c) 2022 Auriga
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+#include "bcm2838-mailbox.h"
+
+#define MBOX_TEST_MESSAGE_ADDRESS 0x10000000
+
+#define TEST_TAG(x) TAG_ ## x
+#define TEST_TAG_TYPE(x) TAG_##x##_t
+
+#define TEST_FN_NAME(test, subtest) \
+ test ## _ ## subtest ## _test
+
+#define SETUP_FN_NAME(test, subtest) \
+ test ## _ ## subtest ## _setup
+
+#define CHECK_FN_NAME(test, subtest) \
+ test ## _ ## subtest ## _spec_check
+
+#define DECLARE_TEST_CASE_SETUP(testname, ...) \
+ void SETUP_FN_NAME(testname, __VA_ARGS__) \
+ (TEST_TAG_TYPE(testname) * tag)
+
+/*----------------------------------------------------------------------------*/
+#define DECLARE_TEST_CASE(testname, ...)
\
+ __attribute__((weak))
\
+ void SETUP_FN_NAME(testname, __VA_ARGS__)
\
+ (TEST_TAG_TYPE(testname) * tag);
\
+ static void CHECK_FN_NAME(testname, __VA_ARGS__)
\
+ (TEST_TAG_TYPE(testname) *tag);
\
+ static void TEST_FN_NAME(testname, __VA_ARGS__)(void) {
\
+ struct {
\
+ MboxBufHeader header;
\
+ TEST_TAG_TYPE(testname) tag;
\
+ uint32_t end_tag;
\
+ } mailbox_buffer = { 0 };
\
+
\
+ QTestState *qts = qtest_init("-machine raspi4b2g");
\
+
\
+ mailbox_buffer.header.size = sizeof(mailbox_buffer);
\
+ mailbox_buffer.header.req_resp_code = MBOX_PROCESS_REQUEST;
\
+
\
+ mailbox_buffer.tag.id = TEST_TAG(testname);
\
+ mailbox_buffer.tag.value_buffer_size = MAX(
\
+ sizeof(mailbox_buffer.tag.request.value),
\
+ sizeof(mailbox_buffer.tag.response.value));
\
+ mailbox_buffer.tag.request.zero = 0;
\
+
\
+ mailbox_buffer.end_tag = TAG_END;
\
+
\
+ if (SETUP_FN_NAME(testname, __VA_ARGS__)) {
\
+ SETUP_FN_NAME(testname, __VA_ARGS__)(&mailbox_buffer.tag);
\
+ }
\
+
\
+ qtest_memwrite(qts, MBOX_TEST_MESSAGE_ADDRESS,
\
+ &mailbox_buffer, sizeof(mailbox_buffer));
\
+ qtest_mbox1_write_message(qts, MBOX_CHANNEL_ID_PROPERTY,
\
+ MBOX_TEST_MESSAGE_ADDRESS);
\
+
\
+ qtest_mbox0_read_message(qts, MBOX_CHANNEL_ID_PROPERTY,
\
+ &mailbox_buffer, sizeof(mailbox_buffer));
\
+
\
+ g_assert_cmphex(mailbox_buffer.header.req_resp_code, ==,
MBOX_SUCCESS);\
+
\
+ g_assert_cmphex(mailbox_buffer.tag.id, ==, TEST_TAG(testname));
\
+ g_assert_cmpint(mailbox_buffer.tag.response.size, ==,
\
+ sizeof(mailbox_buffer.tag.response.value));
\
+ g_assert_cmpint(mailbox_buffer.tag.response.success, ==, 1);
\
+
\
+ CHECK_FN_NAME(testname, __VA_ARGS__)(&mailbox_buffer.tag);
\
+
\
+ qtest_quit(qts);
\
+ }
\
+ static void CHECK_FN_NAME(testname, __VA_ARGS__)
\
+ (TEST_TAG_TYPE(testname) * tag)
+
+/*----------------------------------------------------------------------------*/
+
+#define QTEST_ADD_TEST_CASE(testname, ...)
\
+ qtest_add_func(stringify(/bcm2838/mbox/property/
\
+ TEST_FN_NAME(testname, __VA_ARGS__)-test),
\
+ TEST_FN_NAME(testname, __VA_ARGS__))
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_FIRMWARE_REVISION) {
+ g_assert_cmpint(tag->response.value.revision, ==, FIRMWARE_REVISION);
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_BOARD_REVISION) {
+ g_assert_cmpint(tag->response.value.revision, ==, BOARD_REVISION);
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_ARM_MEMORY) {
+ g_assert_cmphex(tag->response.value.base, ==, ARM_MEMORY_BASE);
+ g_assert_cmphex(tag->response.value.size, ==, ARM_MEMORY_SIZE);
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_VC_MEMORY) {
+ g_assert_cmphex(tag->response.value.base, ==, VC_MEMORY_BASE);
+ g_assert_cmphex(tag->response.value.size, ==, VC_MEMORY_SIZE);
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(SET_DEVICE_POWER_STATE) {
+ g_assert_cmphex(tag->response.value.device_id, ==, DEVICE_ID_UART0);
+ g_assert_cmpint(tag->response.value.enabled, ==, 1);
+ g_assert_cmpint(tag->response.value.wait, ==, 0);
+}
+DECLARE_TEST_CASE_SETUP(SET_DEVICE_POWER_STATE) {
+ tag->request.value.device_id = DEVICE_ID_UART0;
+ tag->request.value.enabled = 1;
+ tag->request.value.wait = 1;
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_CLOCK_STATE) {
+ g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_CORE);
+ g_assert_cmphex(tag->response.value.enabled, ==, 1);
+ g_assert_cmphex(tag->response.value.not_present, ==, 0);
+}
+DECLARE_TEST_CASE_SETUP(GET_CLOCK_STATE) {
+ tag->request.value.clock_id = CLOCK_ID_CORE;
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_CLOCK_RATE, EMMC) {
+ g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_EMMC);
+ g_assert_cmphex(tag->response.value.rate, ==, CLOCK_RATE_EMMC);
+}
+DECLARE_TEST_CASE_SETUP(GET_CLOCK_RATE, EMMC) {
+ tag->request.value.clock_id = CLOCK_ID_EMMC;
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_MAX_CLOCK_RATE, EMMC) {
+ g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_EMMC);
+ g_assert_cmphex(tag->response.value.rate, ==, CLOCK_RATE_EMMC);
+}
+DECLARE_TEST_CASE_SETUP(GET_MAX_CLOCK_RATE, EMMC) {
+ tag->request.value.clock_id = CLOCK_ID_EMMC;
+}
+
+/*----------------------------------------------------------------------------*/
+DECLARE_TEST_CASE(GET_MIN_CLOCK_RATE, EMMC) {
+ g_assert_cmphex(tag->response.value.clock_id, ==, CLOCK_ID_EMMC);
+ g_assert_cmphex(tag->response.value.rate, ==, CLOCK_RATE_EMMC);
+}
+DECLARE_TEST_CASE_SETUP(GET_MIN_CLOCK_RATE, EMMC) {
+ tag->request.value.clock_id = CLOCK_ID_EMMC;
+}
+
+/*----------------------------------------------------------------------------*/
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+
+ QTEST_ADD_TEST_CASE(GET_FIRMWARE_REVISION);
+ QTEST_ADD_TEST_CASE(GET_BOARD_REVISION);
+ QTEST_ADD_TEST_CASE(GET_ARM_MEMORY);
+ QTEST_ADD_TEST_CASE(GET_VC_MEMORY);
+ QTEST_ADD_TEST_CASE(SET_DEVICE_POWER_STATE);
+ QTEST_ADD_TEST_CASE(GET_CLOCK_STATE);
+ QTEST_ADD_TEST_CASE(GET_CLOCK_RATE, EMMC);
+ QTEST_ADD_TEST_CASE(GET_MAX_CLOCK_RATE, EMMC);
+ QTEST_ADD_TEST_CASE(GET_MIN_CLOCK_RATE, EMMC);
+
+ return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 61e9aab835..91393fcbd9 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -217,7 +217,7 @@ qtests_aarch64 = \
['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +
\
(config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test',
'fuzz-xlnx-dp-test'] : []) + \
(config_all_devices.has_key('CONFIG_XLNX_VERSAL') ? ['xlnx-canfd-test'] :
[]) + \
- (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
+ (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test',
'bcm2838-mbox-property-test'] : []) + \
(config_all.has_key('CONFIG_TCG') and
\
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] :
[]) + \
['arm-cpu-features',
--
2.34.1
- [PATCH 38/44] Add mailbox tests tags. Part 2, (continued)
- [PATCH 38/44] Add mailbox tests tags. Part 2, Sergey Kambalin, 2023/07/26
- [PATCH 26/44] Add GENET register structs. Part 4, Sergey Kambalin, 2023/07/26
- [PATCH 19/44] Add RNG200 timer, Sergey Kambalin, 2023/07/26
- [PATCH 28/44] Impl GENET register ops., Sergey Kambalin, 2023/07/26
- [PATCH 32/44] Enable BCM2838 GENET controller, Sergey Kambalin, 2023/07/26
- [PATCH 31/44] Impl GENET RX path, Sergey Kambalin, 2023/07/26
- [PATCH 33/44] Connect RNG200, PCIE and GENET to GIC, Sergey Kambalin, 2023/07/26
- [PATCH 37/44] Add mailbox tests tags. Part 1, Sergey Kambalin, 2023/07/26
- [PATCH 36/44] Add mailbox test constants, Sergey Kambalin, 2023/07/26
- [PATCH 39/44] Add mailbox tests tags. Part 3, Sergey Kambalin, 2023/07/26
- [PATCH 40/44] Add mailbox property tests. Part 1,
Sergey Kambalin <=
- [PATCH 41/44] Add mailbox property tests. Part 2, Sergey Kambalin, 2023/07/26
- [PATCH 42/44] Add mailbox property tests. Part 3, Sergey Kambalin, 2023/07/26
- [PATCH 43/44] Add missed BCM2835 properties, Sergey Kambalin, 2023/07/26
- [PATCH 17/44] Add RNG200 skeleton, Sergey Kambalin, 2023/07/26
- [PATCH 22/44] Add GENET stub, Sergey Kambalin, 2023/07/26
- [PATCH 25/44] Add GENET register structs. Part 3, Sergey Kambalin, 2023/07/26
- [PATCH 34/44] Add Rpi4b boot tests, Sergey Kambalin, 2023/07/26
- [PATCH 44/44] Append added properties to mailbox test, Sergey Kambalin, 2023/07/26