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Re: [PATCH v4 9/9] target/arm: Enable TARGET_TB_PCREL
From: |
Peter Maydell |
Subject: |
Re: [PATCH v4 9/9] target/arm: Enable TARGET_TB_PCREL |
Date: |
Thu, 22 Sep 2022 15:07:53 +0100 |
On Tue, 6 Sept 2022 at 11:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu-param.h | 2 ++
> target/arm/translate.h | 6 ++++
> target/arm/cpu.c | 23 +++++++-------
> target/arm/translate-a64.c | 37 ++++++++++++++++++-----
> target/arm/translate.c | 62 ++++++++++++++++++++++++++++++--------
> 5 files changed, 100 insertions(+), 30 deletions(-)
>
> diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
> index 68ffb12427..ef62371d8f 100644
> --- a/target/arm/cpu-param.h
> +++ b/target/arm/cpu-param.h
> @@ -34,4 +34,6 @@
>
> #define NB_MMU_MODES 15
>
> +#define TARGET_TB_PCREL 1
> +
> #endif
> diff --git a/target/arm/translate.h b/target/arm/translate.h
> index d42059aa1d..7717ea3f45 100644
> --- a/target/arm/translate.h
> +++ b/target/arm/translate.h
> @@ -12,6 +12,12 @@ typedef struct DisasContext {
>
> /* The address of the current instruction being translated. */
> target_ulong pc_curr;
> + /*
> + * For TARGET_TB_PCREL, the value relative to pc_curr against which
> + * offsets must be computed for cpu_pc. -1 if unknown due to jump.
> + */
I'm not really sure what this comment is trying to tell me. Could
you expand it a bit ?
> + target_ulong pc_save;
> + target_ulong pc_cond_save;
> target_ulong page_start;
> uint32_t insn;
> /* Nonzero if this instruction has been conditionally skipped. */
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 047bf3f4ab..f5e74b6c3b 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -64,17 +64,18 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
> void arm_cpu_synchronize_from_tb(CPUState *cs,
> const TranslationBlock *tb)
> {
> - ARMCPU *cpu = ARM_CPU(cs);
> - CPUARMState *env = &cpu->env;
> -
> - /*
> - * It's OK to look at env for the current mode here, because it's
> - * never possible for an AArch64 TB to chain to an AArch32 TB.
> - */
> - if (is_a64(env)) {
> - env->pc = tb_pc(tb);
> - } else {
> - env->regs[15] = tb_pc(tb);
> + /* The program counter is always up to date with TARGET_TB_PCREL. */
Is it?
Is there some documentation in one of the other patchsets about
how TARGET_TB_PCREL works in general and what targets need to do to
support it?
thanks
-- PMM
- [PATCH v4 1/9] target/arm: Introduce curr_insn_len, (continued)
- [PATCH v4 1/9] target/arm: Introduce curr_insn_len, Richard Henderson, 2022/09/06
- [PATCH v4 5/9] target/arm: Change gen_exception_internal to work on displacements, Richard Henderson, 2022/09/06
- [PATCH v4 3/9] target/arm: Change gen_*set_pc_im to gen_*update_pc, Richard Henderson, 2022/09/06
- [PATCH v4 8/9] target/arm: Introduce gen_pc_plus_diff for aarch32, Richard Henderson, 2022/09/06
- [PATCH v4 9/9] target/arm: Enable TARGET_TB_PCREL, Richard Henderson, 2022/09/06
- Re: [PATCH v4 9/9] target/arm: Enable TARGET_TB_PCREL,
Peter Maydell <=