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Re: [PATCH v5 02/24] target/arm: Drop EL3 no EL2 fallbacks
From: |
Peter Maydell |
Subject: |
Re: [PATCH v5 02/24] target/arm: Drop EL3 no EL2 fallbacks |
Date: |
Fri, 6 May 2022 12:36:49 +0100 |
On Thu, 5 May 2022 at 20:15, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo,
> and the local vpidr_regs definition, and rely on the
> squasing to ARM_CP_CONST while registering.
"squashing"
This patch is a behaviour change, which I think is correct, but
it could do with being called out more clearly in the commit
message. Specifically, for v7 with EL3 but not EL2, we used to
register RAZ/WI versions of all the registers in el3_no_el2_cp_reginfo[].
After this change we won't, because we only register el2_cp_reginfo
on v8 no-EL2 CPUs. As it happens, this is correct, because
(as described in the v7A/v7R Arm ARM DDI0406C.d section B3.15.3)
v7 treats these as "PL2-mode system control registers" which are
not supposed to be implemented if the Virtualization Extensions
are not implemented. (There is a weird special case for CNTVOFF,
but luckily it boils down to "it's OK to just UNDEF it".) But
it is a change from what we previously did.
This would be a migration compat break except that we've had
a bug for years that we haven't got round to fixing where migration
of 32-bit CPUs with EL3 implemented doesn't work...
With an improved commit message:
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH v5 00/24] target/arm: Cleanups, new features, new cpus, Richard Henderson, 2022/05/05
- [PATCH v5 07/24] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max, Richard Henderson, 2022/05/05
- [PATCH v5 03/24] target/arm: Merge zcr reginfo, Richard Henderson, 2022/05/05
- [PATCH v5 06/24] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/05/05
- [PATCH v5 02/24] target/arm: Drop EL3 no EL2 fallbacks, Richard Henderson, 2022/05/05
- Re: [PATCH v5 02/24] target/arm: Drop EL3 no EL2 fallbacks,
Peter Maydell <=
- [PATCH v5 05/24] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Richard Henderson, 2022/05/05
- [PATCH v5 08/24] target/arm: Split out aa32_max_features, Richard Henderson, 2022/05/05
- [PATCH v5 01/24] target/arm: Handle cpreg registration for missing EL, Richard Henderson, 2022/05/05
- [PATCH v5 09/24] target/arm: Annotate arm_max_initfn with FEAT identifiers, Richard Henderson, 2022/05/05
- [PATCH v5 04/24] target/arm: Adjust definition of CONTEXTIDR_EL2, Richard Henderson, 2022/05/05
- [PATCH v5 13/24] target/arm: Add minimal RAS registers, Richard Henderson, 2022/05/05
- [PATCH v5 10/24] target/arm: Use field names for manipulating EL2 and EL3 modes, Richard Henderson, 2022/05/05
- [PATCH v5 12/24] target/arm: Enable FEAT_Debugv8p4 for -cpu max, Richard Henderson, 2022/05/05
- [PATCH v5 11/24] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Richard Henderson, 2022/05/05