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[PATCH v3 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
From: |
Edgar E. Iglesias |
Subject: |
[PATCH v3 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF |
Date: |
Wed, 16 Mar 2022 17:46:43 +0100 |
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Connect the ZynqMP CRF - Clock Reset FPD device.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
include/hw/arm/xlnx-zynqmp.h | 2 ++
hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 0552ba18b4..7938f223a4 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -39,6 +39,7 @@
#include "hw/nvram/xlnx-bbram.h"
#include "hw/nvram/xlnx-zynqmp-efuse.h"
#include "hw/or-irq.h"
+#include "hw/misc/xlnx-zynqmp-crf.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -124,6 +125,7 @@ struct XlnxZynqMPState {
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
XlnxCSUDMA qspi_dma;
qemu_or_irq qspi_irq_orgate;
+ XlnxZynqMPCRF crf;
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 47324cdc44..f4575eea7f 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -52,6 +52,9 @@
#define QSPI_DMA_ADDR 0xff0f0800
#define NUM_QSPI_IRQ_LINES 2
+#define CRF_ADDR 0xfd1a0000
+#define CRF_IRQ 120
+
/* Serializer/Deserializer. */
#define SERDES_ADDR 0xfd400000
#define SERDES_SIZE 0x20000
@@ -280,6 +283,18 @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s,
qemu_irq *gic)
sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
}
+static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+
+ object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF);
+ sbd = SYS_BUS_DEVICE(&s->crf);
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, CRF_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
+}
+
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
{
static const struct UnimpInfo {
@@ -684,6 +699,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
xlnx_zynqmp_create_bbram(s, gic_spi);
xlnx_zynqmp_create_efuse(s, gic_spi);
+ xlnx_zynqmp_create_crf(s, gic_spi);
xlnx_zynqmp_create_unimp_mmio(s);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
--
2.25.1
- [PATCH v3 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI, Edgar E. Iglesias, 2022/03/16
- [PATCH v3 2/6] target/arm: Make rvbar settable after realize, Edgar E. Iglesias, 2022/03/16
- [PATCH v3 1/6] hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area, Edgar E. Iglesias, 2022/03/16
- [PATCH v3 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF,
Edgar E. Iglesias <=
- [PATCH v3 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF, Edgar E. Iglesias, 2022/03/16
- [PATCH v3 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control, Edgar E. Iglesias, 2022/03/16
- [PATCH v3 6/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control, Edgar E. Iglesias, 2022/03/16
- Re: [PATCH v3 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI, Peter Maydell, 2022/03/17