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Re: [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control
From: |
Edgar E. Iglesias |
Subject: |
Re: [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control |
Date: |
Mon, 31 Jan 2022 13:17:20 +0100 |
On Mon, Jan 31, 2022 at 12:35:54AM +0100, Philippe Mathieu-Daudé wrote:
> On 31/1/22 00:12, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Add a model of the Xilinx ZynqMP APU Control.
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++
> > hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++++
> > hw/misc/meson.build | 1 +
> > 3 files changed, 349 insertions(+)
> > create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> > create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
> >
> > diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> > b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> > new file mode 100644
> > index 0000000000..44bf264cef
> > --- /dev/null
> > +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> > @@ -0,0 +1,91 @@
> > +/*
> > + * QEMU model of ZynqMP APU Control.
> > + *
> > + * Copyright (c) 2013-2022 Xilinx Inc
> > + * SPDX-License-Identifier: GPL-2.0-or-later
> > + *
> > + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
> > + * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > + *
> > + */
> > +
> > +#include "hw/sysbus.h"
> > +#include "hw/register.h"
> > +#include "target/arm/cpu.h"
> > +
> > +#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
> > +
> > +#define XLNX_ZYNQMP_APU(obj) \
> > + OBJECT_CHECK(XlnxZynqMPAPUCtrl, (obj), TYPE_XLNX_ZYNQMP_APU_CTRL)
> ...
>
> > +#define APU_R_MAX ((R_PWRSTAT) + 1)
> > +
> > +#define NUM_CPUS 4
>
> Hmm isn't it APU_MAX_CPU?
>
Thanks Philippe. Yes, this was a little confusing. The values happen to be the
same but they belong to different models. For example, the apu-ctrl model will
be
reused in Versal.
Anyways, for v2 I've renamed the macros to CRF_MAX_CPU and APU_MAX_CPU
respectevly.
I hope that makes things clearer.
Thanks,
Edgar
[PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control, Edgar E. Iglesias, 2022/01/30
[PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF, Edgar E. Iglesias, 2022/01/30