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[PATCH v3 08/44] target/arm: Implement MVE VNEG
From: |
Peter Maydell |
Subject: |
[PATCH v3 08/44] target/arm: Implement MVE VNEG |
Date: |
Thu, 17 Jun 2021 13:15:52 +0100 |
Implement the MVE VNEG insn (both integer and floating point forms).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-mve.h | 6 ++++++
target/arm/mve.decode | 2 ++
target/arm/mve_helper.c | 12 ++++++++++++
target/arm/translate-mve.c | 15 +++++++++++++++
4 files changed, 35 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 76508d5dd71..733a54d2e3c 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -55,3 +55,9 @@ DEF_HELPER_FLAGS_3(mve_vabsh, TCG_CALL_NO_WG, void, env, ptr,
ptr)
DEF_HELPER_FLAGS_3(mve_vabsw, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vfabsh, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vfabss, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
+DEF_HELPER_FLAGS_3(mve_vnegb, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vnegh, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vnegw, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vfnegh, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vfnegs, TCG_CALL_NO_WG, void, env, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 66963dc1847..82cc0abcb82 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -80,3 +80,5 @@ VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ...
0 @1op_nosz
VABS 1111 1111 1 . 11 .. 01 ... 0 0011 01 . 0 ... 0 @1op
VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op
+VNEG 1111 1111 1 . 11 .. 01 ... 0 0011 11 . 0 ... 0 @1op
+VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index eaf750ead0b..7ba6a8a2d9e 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -309,3 +309,15 @@ DO_1OP(vabsw, 4, int32_t, DO_ABS)
/* We can do these 64 bits at a time */
DO_1OP(vfabsh, 8, uint64_t, DO_FABSH)
DO_1OP(vfabss, 8, uint64_t, DO_FABSS)
+
+#define DO_NEG(N) (-(N))
+#define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000))
+#define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000))
+
+DO_1OP(vnegb, 1, int8_t, DO_NEG)
+DO_1OP(vnegh, 2, int16_t, DO_NEG)
+DO_1OP(vnegw, 4, int32_t, DO_NEG)
+
+/* We can do these 64 bits at a time */
+DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
+DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 90996813a85..ad2e4af2844 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -200,6 +200,7 @@ static bool do_1op(DisasContext *s, arg_1op *a,
MVEGenOneOpFn fn)
DO_1OP(VCLZ, vclz)
DO_1OP(VCLS, vcls)
DO_1OP(VABS, vabs)
+DO_1OP(VNEG, vneg)
static bool trans_VREV16(DisasContext *s, arg_1op *a)
{
@@ -252,3 +253,17 @@ static bool trans_VABS_fp(DisasContext *s, arg_1op *a)
}
return do_1op(s, a, fns[a->size]);
}
+
+static bool trans_VNEG_fp(DisasContext *s, arg_1op *a)
+{
+ static MVEGenOneOpFn * const fns[] = {
+ NULL,
+ gen_helper_mve_vfnegh,
+ gen_helper_mve_vfnegs,
+ NULL,
+ };
+ if (!dc_isar_feature(aa32_mve_fp, s)) {
+ return false;
+ }
+ return do_1op(s, a, fns[a->size]);
+}
--
2.20.1
- Re: [PATCH v3 01/44] target/arm: Implement MVE VLDR/VSTR (non-widening forms), (continued)
- [PATCH v3 03/44] target/arm: Implement MVE VCLZ, Peter Maydell, 2021/06/17
- [PATCH v3 04/44] target/arm: Implement MVE VCLS, Peter Maydell, 2021/06/17
- [PATCH v3 06/44] target/arm: Implement MVE VMVN (register), Peter Maydell, 2021/06/17
- [PATCH v3 05/44] target/arm: Implement MVE VREV16, VREV32, VREV64, Peter Maydell, 2021/06/17
- [PATCH v3 09/44] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64, Peter Maydell, 2021/06/17
- [PATCH v3 08/44] target/arm: Implement MVE VNEG,
Peter Maydell <=
- [PATCH v3 07/44] target/arm: Implement MVE VABS, Peter Maydell, 2021/06/17
- [PATCH v3 12/44] target/arm: Implement MVE VADD, VSUB, VMUL, Peter Maydell, 2021/06/17
- [PATCH v3 11/44] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR, Peter Maydell, 2021/06/17
- [PATCH v3 10/44] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/17
- [PATCH v3 14/44] target/arm: Implement MVE VRMULH, Peter Maydell, 2021/06/17
- [PATCH v3 13/44] target/arm: Implement MVE VMULH, Peter Maydell, 2021/06/17
- [PATCH v3 17/44] target/arm: Implement MVE VHADD, VHSUB, Peter Maydell, 2021/06/17
- [PATCH v3 15/44] target/arm: Implement MVE VMAX, VMIN, Peter Maydell, 2021/06/17
- [PATCH v3 18/44] target/arm: Implement MVE VMULL, Peter Maydell, 2021/06/17
- [PATCH v3 16/44] target/arm: Implement MVE VABD, Peter Maydell, 2021/06/17