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[PATCH 45/55] target/arm: Implement MVE VSHL insn
From: |
Peter Maydell |
Subject: |
[PATCH 45/55] target/arm: Implement MVE VSHL insn |
Date: |
Mon, 7 Jun 2021 17:58:11 +0100 |
Implement the MVE VSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-mve.h | 8 ++++++++
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c | 30 ++++++++++++++++++++++++++++++
target/arm/translate-mve.c | 2 ++
4 files changed, 43 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index a2f9916b24e..6ef01d367b4 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -171,6 +171,14 @@ DEF_HELPER_FLAGS_4(mve_vqsubub, TCG_CALL_NO_WG, void, env,
ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index e78eab6d659..ebf156b46b5 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -130,6 +130,9 @@ VQADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 1
... 0 @2op
VQSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op
VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op
+VSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev
+VSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev
+
VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index b7f9af4067b..c95d5a0fd8e 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -508,6 +508,36 @@ DO_2OP_U(vhaddu, do_vhadd_u)
DO_2OP_S(vhsubs, do_vhsub_s)
DO_2OP_U(vhsubu, do_vhsub_u)
+static inline uint32_t do_ushl(uint32_t n, int8_t shift, int esize)
+{
+ if (shift >= esize || shift <= -esize) {
+ return 0;
+ } else if (shift < 0) {
+ return n >> -shift;
+ } else {
+ return n << shift;
+ }
+}
+
+static inline int32_t do_sshl(int32_t n, int8_t shift, int esize)
+{
+ if (shift >= esize) {
+ return 0;
+ } else if (shift <= -esize) {
+ return n >> (esize - 1);
+ } else if (shift < 0) {
+ return n >> -shift;
+ } else {
+ return n << shift;
+ }
+}
+
+#define DO_VSHLS(N, M) do_sshl(N, M, sizeof(N) * 8)
+#define DO_VSHLU(N, M) do_ushl(N, M, sizeof(N) * 8)
+
+DO_2OP_S(vshls, DO_VSHLS)
+DO_2OP_U(vshlu, DO_VSHLU)
+
static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool
*s)
{
if (val > max) {
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index bea561726ea..6eaa99bc0f5 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -421,6 +421,8 @@ DO_2OP(VQADD_S, vqadds)
DO_2OP(VQADD_U, vqaddu)
DO_2OP(VQSUB_S, vqsubs)
DO_2OP(VQSUB_U, vqsubu)
+DO_2OP(VSHL_S, vshls)
+DO_2OP(VSHL_U, vshlu)
DO_2OP(VQSHL_S, vqshls)
DO_2OP(VQSHL_U, vqshlu)
DO_2OP(VQRSHL_S, vqrshls)
--
2.20.1
- Re: [PATCH 40/55] target/arm: Implement MVE VQDMULL scalar, (continued)
- [PATCH 41/55] target/arm: Implement MVE VQDMULH, VQRDMULH (vector), Peter Maydell, 2021/06/07
- [PATCH 38/55] target/arm: Implement MVE VQADD and VQSUB, Peter Maydell, 2021/06/07
- [PATCH 44/55] target/arm: Implement MVE VQRSHL, Peter Maydell, 2021/06/07
- [PATCH 32/55] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/07
- [PATCH 45/55] target/arm: Implement MVE VSHL insn,
Peter Maydell <=
- [PATCH 42/55] target/arm: Implement MVE VQADD, VQSUB (vector), Peter Maydell, 2021/06/07
- [PATCH 46/55] target/arm: Implement MVE VRSHL, Peter Maydell, 2021/06/07
- [PATCH 33/55] target/arm: Implement MVE VADD (scalar), Peter Maydell, 2021/06/07
- [PATCH 50/55] target/arm: Implement MVE VRHADD, Peter Maydell, 2021/06/07
- [PATCH 49/55] target/arm: Implement MVE VQDMULL (vector), Peter Maydell, 2021/06/07