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[PATCH v7 87/92] target/arm: Split out do_neon_ddda
From: |
Richard Henderson |
Subject: |
[PATCH v7 87/92] target/arm: Split out do_neon_ddda |
Date: |
Mon, 24 May 2021 18:03:53 -0700 |
Split out a helper that can handle the 4-register
format for helpers shared with SVE.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-neon.c | 90 ++++++++++++++++---------------------
1 file changed, 38 insertions(+), 52 deletions(-)
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index 9f7a88aab1..dfa33912ab 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -151,6 +151,36 @@ static void neon_store_element64(int reg, int ele, MemOp
size, TCGv_i64 var)
}
}
+static bool do_neon_ddda(DisasContext *s, int q, int vd, int vn, int vm,
+ int data, gen_helper_gvec_4 *fn_gvec)
+{
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (((vd | vn | vm) & 0x10) && !dc_isar_feature(aa32_simd_r32, s)) {
+ return false;
+ }
+
+ /*
+ * UNDEF accesses to odd registers for each bit of Q.
+ * Q will be 0b111 for all Q-reg instructions, otherwise
+ * when we have mixed Q- and D-reg inputs.
+ */
+ if (((vd & 1) * 4 | (vn & 1) * 2 | (vm & 1)) & q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ int opr_sz = q ? 16 : 8;
+ tcg_gen_gvec_4_ool(vfp_reg_offset(1, vd),
+ vfp_reg_offset(1, vn),
+ vfp_reg_offset(1, vm),
+ vfp_reg_offset(1, vd),
+ opr_sz, opr_sz, data, fn_gvec);
+ return true;
+}
+
static bool do_neon_ddda_fpst(DisasContext *s, int q, int vd, int vn, int vm,
int data, ARMFPStatusFlavour fp_flavour,
gen_helper_gvec_4_ptr *fn_gvec_ptr)
@@ -241,35 +271,13 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
{
- int opr_sz;
- gen_helper_gvec_4 *fn_gvec;
-
if (!dc_isar_feature(aa32_dp, s)) {
return false;
}
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vn | a->vm | a->vd) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- opr_sz = (1 + a->q) * 8;
- fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
- tcg_gen_gvec_4_ool(vfp_reg_offset(1, a->vd),
- vfp_reg_offset(1, a->vn),
- vfp_reg_offset(1, a->vm),
- vfp_reg_offset(1, a->vd),
- opr_sz, opr_sz, 0, fn_gvec);
- return true;
+ return do_neon_ddda(s, a->q * 7, a->vd, a->vn, a->vm, 0,
+ a->u
+ ? gen_helper_gvec_udot_b
+ : gen_helper_gvec_sdot_b);
}
static bool trans_VFML(DisasContext *s, arg_VFML *a)
@@ -323,35 +331,13 @@ static bool trans_VCMLA_scalar(DisasContext *s,
arg_VCMLA_scalar *a)
static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
{
- gen_helper_gvec_4 *fn_gvec;
- int opr_sz;
-
if (!dc_isar_feature(aa32_dp, s)) {
return false;
}
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vn) & 0x10)) {
- return false;
- }
-
- if ((a->vd | a->vn) & a->q) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
- opr_sz = (1 + a->q) * 8;
- tcg_gen_gvec_4_ool(vfp_reg_offset(1, a->vd),
- vfp_reg_offset(1, a->vn),
- vfp_reg_offset(1, a->vm),
- vfp_reg_offset(1, a->vd),
- opr_sz, opr_sz, a->index, fn_gvec);
- return true;
+ return do_neon_ddda(s, a->q * 6, a->vd, a->vn, a->vm, a->index,
+ a->u
+ ? gen_helper_gvec_udot_idx_b
+ : gen_helper_gvec_sdot_idx_b);
}
static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
--
2.25.1
- [PATCH v7 75/92] target/arm: Implement SVE2 FLOGB, (continued)
- [PATCH v7 75/92] target/arm: Implement SVE2 FLOGB, Richard Henderson, 2021/05/24
- [PATCH v7 77/92] target/arm: Tidy do_ldrq, Richard Henderson, 2021/05/24
- [PATCH v7 79/92] target/arm: Implement 128-bit ZIP, UZP, TRN, Richard Henderson, 2021/05/24
- [PATCH v7 76/92] target/arm: Share table of sve load functions, Richard Henderson, 2021/05/24
- [PATCH v7 78/92] target/arm: Implement SVE2 LD1RO, Richard Henderson, 2021/05/24
- [PATCH v7 81/92] target/arm: Move endian adjustment macros to vec_internal.h, Richard Henderson, 2021/05/24
- [PATCH v7 82/92] target/arm: Implement SVE2 fp multiply-add long, Richard Henderson, 2021/05/24
- [PATCH v7 80/92] target/arm: Implement SVE2 bitwise shift immediate, Richard Henderson, 2021/05/24
- [PATCH v7 86/92] target/arm: Fix decode for VDOT (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 83/92] target/arm: Implement aarch64 SUDOT, USDOT, Richard Henderson, 2021/05/24
- [PATCH v7 87/92] target/arm: Split out do_neon_ddda,
Richard Henderson <=
- [PATCH v7 85/92] target/arm: Remove unused fpst from VDOT_scalar, Richard Henderson, 2021/05/24
- [PATCH v7 88/92] target/arm: Split decode of VSDOT and VUDOT, Richard Henderson, 2021/05/24
- [PATCH v7 90/92] target/arm: Implement integer matrix multiply accumulate, Richard Henderson, 2021/05/24
- [PATCH v7 89/92] target/arm: Implement aarch32 VSUDOT, VUSDOT, Richard Henderson, 2021/05/24
- [PATCH v7 84/92] target/arm: Split out do_neon_ddda_fpst, Richard Henderson, 2021/05/24
- [PATCH v7 91/92] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions, Richard Henderson, 2021/05/24
- [PATCH v7 92/92] target/arm: Enable SVE2 and related extensions, Richard Henderson, 2021/05/24
- Re: [PATCH v7 00/92] target/arm: Implement SVE2, no-reply, 2021/05/24
- Re: [PATCH v7 00/92] target/arm: Implement SVE2, Peter Maydell, 2021/05/25