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[PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension
From: |
remi . denis . courmont |
Subject: |
[PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension |
Date: |
Tue, 12 Jan 2021 12:45:09 +0200 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
This adds handling for the SCR_EL3.EEL2 bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
---
target/arm/cpu.c | 2 +-
target/arm/cpu.h | 8 ++++++--
target/arm/helper.c | 19 ++++++++++++++++---
target/arm/translate.c | 14 ++++++++++++--
4 files changed, 35 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5530874686..b85b644941 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -480,7 +480,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned
int excp_idx,
* masked from Secure state. The HCR and SCR settings
* don't affect the masking logic, only the interrupt routing.
*/
- if (target_el == 3 || !secure) {
+ if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) {
unmasked = true;
}
} else {
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e605791e47..df510114f6 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2094,7 +2094,10 @@ static inline bool arm_is_secure(CPUARMState *env)
static inline bool arm_is_el2_enabled(CPUARMState *env)
{
if (arm_feature(env, ARM_FEATURE_EL2)) {
- return !arm_is_secure_below_el3(env);
+ if (arm_is_secure_below_el3(env)) {
+ return (env->cp15.scr_el3 & SCR_EEL2) != 0;
+ }
+ return true;
}
return false;
}
@@ -2141,7 +2144,8 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int
el)
return aa64;
}
- if (arm_feature(env, ARM_FEATURE_EL3)) {
+ if (arm_feature(env, ARM_FEATURE_EL3) &&
+ ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7648f6fb97..32fc72d9ed 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -532,6 +532,9 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState
*env,
return CP_ACCESS_OK;
}
if (arm_is_secure_below_el3(env)) {
+ if (env->cp15.scr_el3 & SCR_EEL2) {
+ return CP_ACCESS_TRAP_EL2;
+ }
return CP_ACCESS_TRAP_EL3;
}
/* This will be EL1 NS and EL2 NS, which just UNDEF */
@@ -2029,6 +2032,9 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
if (cpu_isar_feature(aa64_pauth, cpu)) {
valid_mask |= SCR_API | SCR_APK;
}
+ if (cpu_isar_feature(aa64_sel2, cpu)) {
+ valid_mask |= SCR_EEL2;
+ }
if (cpu_isar_feature(aa64_mte, cpu)) {
valid_mask |= SCR_ATA;
}
@@ -3387,13 +3393,16 @@ static CPAccessResult ats_access(CPUARMState *env,
const ARMCPRegInfo *ri,
bool isread)
{
if (ri->opc2 & 4) {
- /* The ATS12NSO* operations must trap to EL3 if executed in
+ /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
* Secure EL1 (which can only happen if EL3 is AArch64).
* They are simply UNDEF if executed from NS EL1.
* They function normally from EL2 or EL3.
*/
if (arm_current_el(env) == 1) {
if (arm_is_secure_below_el3(env)) {
+ if (env->cp15.scr_el3 & SCR_EEL2) {
+ return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
+ }
return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
}
return CP_ACCESS_TRAP_UNCATEGORIZED;
@@ -3656,7 +3665,8 @@ static void ats1h_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
- if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
+ if (arm_current_el(env) == 3 &&
+ !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) {
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
@@ -5755,12 +5765,15 @@ static CPAccessResult nsacr_access(CPUARMState *env,
const ARMCPRegInfo *ri,
bool isread)
{
/* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
- * At Secure EL1 it traps to EL3.
+ * At Secure EL1 it traps to EL3 or EL2.
*/
if (arm_current_el(env) == 3) {
return CP_ACCESS_OK;
}
if (arm_is_secure_below_el3(env)) {
+ if (env->cp15.scr_el3 & SCR_EEL2) {
+ return CP_ACCESS_TRAP_EL2;
+ }
return CP_ACCESS_TRAP_EL3;
}
/* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8b6b7355c9..688cd41684 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2832,9 +2832,19 @@ static bool msr_banked_access_decode(DisasContext *s,
int r, int sysm, int rn,
}
if (s->current_el == 1) {
/* If we're in Secure EL1 (which implies that EL3 is AArch64)
- * then accesses to Mon registers trap to EL3
+ * then accesses to Mon registers trap to Secure EL2, if it exists,
+ * otherwise EL3.
*/
- TCGv_i32 tcg_el = tcg_const_i32(3);
+ TCGv_i32 tcg_el;
+
+ if (dc_isar_feature(aa64_sel2, s)) {
+ /* Target EL is EL<3 minus SCR_EL3.EEL2> */
+ tcg_el = load_cpu_field(cp15.scr_el3);
+ tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);
+ tcg_gen_addi_i32(tcg_el, tcg_el, 3);
+ } else {
+ tcg_el = tcg_const_i32(3);
+ }
gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
tcg_temp_free_i32(tcg_el);
--
2.30.0
- [PATCH 05/19] target/arm: factor MDCR_EL2 common handling, (continued)
- [PATCH 05/19] target/arm: factor MDCR_EL2 common handling, remi . denis . courmont, 2021/01/12
- [PATCH 03/19] target/arm: use arm_is_el2_enabled() where applicable, remi . denis . courmont, 2021/01/12
- [PATCH 10/19] target/arm: handle VMID change in secure state, remi . denis . courmont, 2021/01/12
- [PATCH 06/19] target/arm: declare new AA64PFR0 bit-fields, remi . denis . courmont, 2021/01/12
- [PATCH 04/19] target/arm: use arm_hcr_el2_eff() where applicable, remi . denis . courmont, 2021/01/12
- [PATCH 11/19] target/arm: do S1_ptw_translate() before address space lookup, remi . denis . courmont, 2021/01/12
- [PATCH 08/19] target/arm: add MMU stage 1 for Secure EL2, remi . denis . courmont, 2021/01/12
- [PATCH 09/19] target/arm: add ARMv8.4-SEL2 system registers, remi . denis . courmont, 2021/01/12
- [PATCH 07/19] target/arm: add 64-bit S-EL2 to EL exception table, remi . denis . courmont, 2021/01/12
- [PATCH 19/19] target/arm: refactor vae1_tlbmask(), remi . denis . courmont, 2021/01/12
- [PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension,
remi . denis . courmont <=
- [PATCH 15/19] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, remi . denis . courmont, 2021/01/12
- [PATCH 13/19] target/arm: generalize 2-stage page-walk condition, remi . denis . courmont, 2021/01/12
- [PATCH 14/19] target/arm: secure stage 2 translation regime, remi . denis . courmont, 2021/01/12
- [PATCH 12/19] target/arm: translate NS bit in page-walks, remi . denis . courmont, 2021/01/12
- [PATCH 18/19] target/arm: enable Secure EL2 in max CPU, remi . denis . courmont, 2021/01/12
- [PATCH 16/19] target/arm: revector to run-time pick target EL, remi . denis . courmont, 2021/01/12