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[PATCH v8 17/45] target/arm: Restrict the values of DCZID.BS under TCG
From: |
Richard Henderson |
Subject: |
[PATCH v8 17/45] target/arm: Restrict the values of DCZID.BS under TCG |
Date: |
Tue, 23 Jun 2020 12:36:30 -0700 |
We can simplify our DC_ZVA if we recognize that the largest BS
that we actually use in system mode is 64. Let us just assert
that it fits within TARGET_PAGE_SIZE.
For DC_GVA and STZGM, we want to be able to write whole bytes
of tag memory, so assert that BS is >= 2 * TAG_GRANULE, or 32.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 10677c0c23..f09efc4370 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1758,6 +1758,30 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
}
#endif
+ if (tcg_enabled()) {
+ int dcz_blocklen = 4 << cpu->dcz_blocksize;
+
+ /*
+ * We only support DCZ blocklen that fits on one page.
+ *
+ * Architectually this is always true. However TARGET_PAGE_SIZE
+ * is variable and, for compatibility with -machine virt-2.7,
+ * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
+ * But even then, while the largest architectural DCZ blocklen
+ * is 2KiB, no cpu actually uses such a large blocklen.
+ */
+ assert(dcz_blocklen <= TARGET_PAGE_SIZE);
+
+ /*
+ * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
+ * both nibbles of each byte storing tag data may be written at once.
+ * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
+ */
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ assert(dcz_blocklen >= 2 * TAG_GRANULE);
+ }
+ }
+
qemu_init_vcpu(cs);
cpu_reset(cs);
--
2.25.1
- Re: [PATCH v8 10/45] target/arm: Revise decoding for disas_add_sub_imm, (continued)
- [PATCH v8 12/45] target/arm: Implement the GMI instruction, Richard Henderson, 2020/06/23
- [PATCH v8 11/45] target/arm: Implement the ADDG, SUBG instructions, Richard Henderson, 2020/06/23
- [PATCH v8 13/45] target/arm: Implement the SUBP instruction, Richard Henderson, 2020/06/23
- [PATCH v8 14/45] target/arm: Define arm_cpu_do_unaligned_access for user-only, Richard Henderson, 2020/06/23
- [PATCH v8 16/45] target/arm: Implement the STGP instruction, Richard Henderson, 2020/06/23
- [PATCH v8 15/45] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2020/06/23
- [PATCH v8 17/45] target/arm: Restrict the values of DCZID.BS under TCG,
Richard Henderson <=
- [PATCH v8 18/45] target/arm: Simplify DC_ZVA, Richard Henderson, 2020/06/23
- [PATCH v8 19/45] target/arm: Implement the LDGM, STGM, STZGM instructions, Richard Henderson, 2020/06/23
- [PATCH v8 20/45] target/arm: Implement the access tag cache flushes, Richard Henderson, 2020/06/23
- [PATCH v8 21/45] target/arm: Move regime_el to internals.h, Richard Henderson, 2020/06/23
- [PATCH v8 22/45] target/arm: Move regime_tcr to internals.h, Richard Henderson, 2020/06/23
- [PATCH v8 23/45] target/arm: Add gen_mte_check1, Richard Henderson, 2020/06/23
- [PATCH v8 24/45] target/arm: Add gen_mte_checkN, Richard Henderson, 2020/06/23
- [PATCH v8 25/45] target/arm: Implement helper_mte_check1, Richard Henderson, 2020/06/23
- [PATCH v8 26/45] target/arm: Implement helper_mte_checkN, Richard Henderson, 2020/06/23