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[PATCH v2 014/100] target/arm: Add ID_AA64ZFR0 fields and isar_feature_a
From: |
Richard Henderson |
Subject: |
[PATCH v2 014/100] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 |
Date: |
Wed, 17 Jun 2020 21:25:18 -0700 |
Will be used for SVE2 isa subset enablement.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Do not read zfr0 from kvm unless sve is available.
---
target/arm/cpu.h | 16 ++++++++++++++++
target/arm/helper.c | 3 +--
target/arm/kvm64.c | 11 +++++++++++
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 677584e5da..e9f56e67c7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -907,6 +907,7 @@ struct ARMCPU {
uint64_t id_aa64mmfr2;
uint64_t id_aa64dfr0;
uint64_t id_aa64dfr1;
+ uint64_t id_aa64zfr0;
} isar;
uint64_t midr;
uint32_t revidr;
@@ -1866,6 +1867,16 @@ FIELD(ID_AA64DFR0, PMSVER, 32, 4)
FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
+FIELD(ID_AA64ZFR0, AES, 4, 4)
+FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
+FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
+FIELD(ID_AA64ZFR0, SHA3, 32, 4)
+FIELD(ID_AA64ZFR0, SM4, 40, 4)
+FIELD(ID_AA64ZFR0, I8MM, 44, 4)
+FIELD(ID_AA64ZFR0, F32MM, 52, 4)
+FIELD(ID_AA64ZFR0, F64MM, 56, 4)
+
FIELD(ID_DFR0, COPDBG, 0, 4)
FIELD(ID_DFR0, COPSDBG, 4, 4)
FIELD(ID_DFR0, MMAPDBG, 8, 4)
@@ -3846,6 +3857,11 @@ static inline bool isar_feature_aa64_tts2uxn(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
}
+static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 972a766730..51b97c2196 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7232,8 +7232,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- /* At present, only SVEver == 0 is defined anyway. */
- .resetvalue = 0 },
+ .resetvalue = cpu->isar.id_aa64zfr0 },
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index f09ed9f4df..ff46d8418d 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -549,6 +549,17 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf)
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
ARM64_SYS_REG(3, 0, 0, 7, 2));
+ /*
+ * Before v5.1, KVM did not support SVE and did not expose
+ * ID_AA64ZFR0_EL1 even as RAZ. Afterward, KVM still does
+ * not expose the register to "user" requests like this
+ * unless the host supports SVE.
+ */
+ if (isar_feature_aa64_sve(&ahcf->isar)) {
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
+ ARM64_SYS_REG(3, 0, 0, 4, 4));
+ }
+
/*
* Note that if AArch32 support is not present in the host,
* the AArch32 sysregs are present to be read, but will
--
2.25.1
- [PATCH v2 004/100] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, (continued)
- [PATCH v2 004/100] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, Richard Henderson, 2020/06/18
- [PATCH v2 005/100] target/arm: Rearrange {sve, fp}_check_access assert, Richard Henderson, 2020/06/18
- [PATCH v2 006/100] target/arm: Merge do_vector2_p into do_mov_p, Richard Henderson, 2020/06/18
- [PATCH v2 007/100] target/arm: Clean up 4-operand predicate expansion, Richard Henderson, 2020/06/18
- [PATCH v2 008/100] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp, Richard Henderson, 2020/06/18
- [PATCH v2 009/100] target/arm: Split out gen_gvec_ool_zzzp, Richard Henderson, 2020/06/18
- [PATCH v2 011/100] target/arm: Split out gen_gvec_ool_zzp, Richard Henderson, 2020/06/18
- [PATCH v2 012/100] target/arm: Split out gen_gvec_ool_zzz, Richard Henderson, 2020/06/18
- [PATCH v2 010/100] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Richard Henderson, 2020/06/18
- [PATCH v2 013/100] target/arm: Split out gen_gvec_ool_zz, Richard Henderson, 2020/06/18
- [PATCH v2 014/100] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2,
Richard Henderson <=
- [PATCH v2 016/100] target/arm: Implement SVE2 Integer Multiply - Unpredicated, Richard Henderson, 2020/06/18
- [PATCH v2 015/100] target/arm: Enable SVE2 and some extensions, Richard Henderson, 2020/06/18
- [PATCH v2 018/100] target/arm: Implement SVE2 integer unary operations (predicated), Richard Henderson, 2020/06/18
- [PATCH v2 017/100] target/arm: Implement SVE2 integer pairwise add and accumulate long, Richard Henderson, 2020/06/18
- [PATCH v2 019/100] target/arm: Split out saturating/rounding shifts from neon, Richard Henderson, 2020/06/18
- [PATCH v2 020/100] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated), Richard Henderson, 2020/06/18
- [PATCH v2 021/100] target/arm: Implement SVE2 integer halving add/subtract (predicated), Richard Henderson, 2020/06/18
- [PATCH v2 022/100] target/arm: Implement SVE2 integer pairwise arithmetic, Richard Henderson, 2020/06/18
- [PATCH v2 023/100] target/arm: Implement SVE2 saturating add/subtract (predicated), Richard Henderson, 2020/06/18
- [PATCH v2 024/100] target/arm: Implement SVE2 integer add/subtract long, Richard Henderson, 2020/06/18