[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames
From: |
Sai Pavan Boddu |
Subject: |
RE: [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames |
Date: |
Wed, 13 May 2020 05:15:57 +0000 |
Thanks for review edgar!
Regards,
Sai pavan
> -----Original Message-----
> From: Edgar E. Iglesias <address@hidden>
> Sent: Tuesday, May 12, 2020 8:50 PM
> To: Sai Pavan Boddu <address@hidden>
> Cc: Alistair Francis <address@hidden>; Peter Maydell
> <address@hidden>; Jason Wang <address@hidden>; Markus
> Armbruster <address@hidden>; Philippe Mathieu-Daudé
> <address@hidden>; Tong Ho <address@hidden>; Ramon Fried
> <address@hidden>; address@hidden; qemu-
> address@hidden
> Subject: Re: [PATCH v5 08/12] net: cadence_gem: Add support for jumbo
> frames
>
> On Tue, May 12, 2020 at 08:24:50PM +0530, Sai Pavan Boddu wrote:
> > Add a property "jumbo-max-len", which sets default value of jumbo
> > frames up to 16,383 bytes. Add Frame length checks for standard and
> > jumbo frames.
>
> Reviewed-by: Edgar E. Iglesias <address@hidden>
>
>
>
> >
> > Signed-off-by: Sai Pavan Boddu <address@hidden>
> > ---
> > hw/net/cadence_gem.c | 51
> +++++++++++++++++++++++++++++++++++++++-----
> > include/hw/net/cadence_gem.h | 4 +++-
> > 2 files changed, 49 insertions(+), 6 deletions(-)
> >
> > diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index
> > f6ff27c..eb02946 100644
> > --- a/hw/net/cadence_gem.c
> > +++ b/hw/net/cadence_gem.c
> > @@ -61,6 +61,7 @@
> > #define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */
> > #define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and
> Forward */
> > #define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and
> Forward */
> > +#define GEM_JUMBO_MAX_LEN (0x00000048 / 4) /* Max Jumbo Frame
> Size */
> > #define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */
> > #define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */
> > #define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */
> > @@ -212,10 +213,12 @@
> > #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with
> len err */
> > #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer
> offset mask */
> > #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift
> */
> > +#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes
> frame */
> > #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash
> match */
> > #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if
> hash match */
> > #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast
> packets */
> > #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
> > +#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames
> enable */
> >
> > #define GEM_DMACFG_ADDR_64B (1U << 30)
> > #define GEM_DMACFG_TX_BD_EXT (1U << 29)
> > @@ -233,6 +236,7 @@
> >
> > /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
> > #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
> > +#define GEM_INT_AMBA_ERR 0x00000040
> > #define GEM_INT_TXUSED 0x00000008
> > #define GEM_INT_RXUSED 0x00000004
> > #define GEM_INT_RXCMPL 0x00000002
> > @@ -453,6 +457,24 @@ static inline void rx_desc_set_sar(uint32_t
> > *desc, int sar_idx)
> > /* The broadcast MAC address: 0xFFFFFFFFFFFF */ static const uint8_t
> > broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
> >
> > +static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) {
> > + uint32_t size;
> > + if (s->regs[GEM_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
> > + size = s->regs[GEM_JUMBO_MAX_LEN];
> > + if (size > s->jumbo_max_len) {
> > + size = s->jumbo_max_len;
> > + qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN
> reg cannot be"
> > + " greater than 0x%" PRIx32 "\n", s->jumbo_max_len);
> > + }
> > + } else if (tx) {
> > + size = 1518;
> > + } else {
> > + size = s->regs[GEM_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 :
> 1518;
> > + }
> > + return size;
> > +}
> > +
> > static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) {
> > if (q == 0) {
> > @@ -1016,6 +1038,12 @@ static ssize_t gem_receive(NetClientState *nc,
> const uint8_t *buf, size_t size)
> > /* Find which queue we are targeting */
> > q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
> >
> > + if (size > gem_get_max_buf_len(s, false)) {
> > + qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n");
> > + gem_set_isr(s, q, GEM_INT_AMBA_ERR);
> > + return -1;
> > + }
> > +
> > while (bytes_to_copy) {
> > hwaddr desc_addr;
> >
> > @@ -1196,12 +1224,13 @@ static void gem_transmit(CadenceGEMState
> *s)
> > break;
> > }
> >
> > - if (tx_desc_get_length(desc) > MAX_FRAME_SIZE -
> > + if (tx_desc_get_length(desc) > gem_get_max_buf_len(s,
> > + true) -
> > (p - s->tx_packet)) {
> > - DB_PRINT("TX descriptor @ 0x%" HWADDR_PRIx \
> > - " too large: size 0x%x space 0x%zx\n",
> > + qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \
> > + HWADDR_PRIx " too large: size 0x%x space
> > + 0x%zx\n",
> > packet_desc_addr, tx_desc_get_length(desc),
> > - MAX_FRAME_SIZE - (p - s->tx_packet));
> > + gem_get_max_buf_len(s, true) - (p -
> > s->tx_packet));
> > + gem_set_isr(s, q, GEM_INT_AMBA_ERR);
> > break;
> > }
> >
> > @@ -1343,9 +1372,10 @@ static void gem_reset(DeviceState *d)
> > s->regs[GEM_RXPARTIALSF] = 0x000003ff;
> > s->regs[GEM_MODID] = s->revision;
> > s->regs[GEM_DESCONF] = 0x02500111;
> > - s->regs[GEM_DESCONF2] = 0x2ab13fff;
> > + s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
> > s->regs[GEM_DESCONF5] = 0x002f2045;
> > s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
> > + s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len;
> >
> > if (s->num_priority_queues > 1) {
> > queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
> > @@ -1516,6 +1546,9 @@ static void gem_write(void *opaque, hwaddr
> offset, uint64_t val,
> > s->regs[GEM_IMR] &= ~val;
> > gem_update_int_status(s);
> > break;
> > + case GEM_JUMBO_MAX_LEN:
> > + s->regs[GEM_JUMBO_MAX_LEN] = val &
> MAX_JUMBO_FRAME_SIZE_MASK;
> > + break;
> > case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
> > s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &=
> ~val;
> > gem_update_int_status(s);
> > @@ -1610,6 +1643,12 @@ static void gem_realize(DeviceState *dev, Error
> > **errp)
> >
> > s->nic = qemu_new_nic(&net_gem_info, &s->conf,
> > object_get_typename(OBJECT(dev)), dev->id,
> > s);
> > +
> > + if (s->jumbo_max_len > MAX_FRAME_SIZE) {
> > + error_setg(errp, "jumbo-max-len is greater than %d",
> > + MAX_FRAME_SIZE);
> > + return;
> > + }
> > }
> >
> > static void gem_init(Object *obj)
> > @@ -1659,6 +1698,8 @@ static Property gem_properties[] = {
> > num_type1_screeners, 4),
> > DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
> > num_type2_screeners, 4),
> > + DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
> > + jumbo_max_len, 10240),
> > DEFINE_PROP_END_OF_LIST(),
> > };
> >
> > diff --git a/include/hw/net/cadence_gem.h
> > b/include/hw/net/cadence_gem.h index eddac70..54e646f 100644
> > --- a/include/hw/net/cadence_gem.h
> > +++ b/include/hw/net/cadence_gem.h
> > @@ -40,7 +40,8 @@
> > #define MAX_TYPE1_SCREENERS 16
> > #define MAX_TYPE2_SCREENERS 16
> >
> > -#define MAX_FRAME_SIZE 2048
> > +#define MAX_JUMBO_FRAME_SIZE_MASK 0x3FFF #define
> MAX_FRAME_SIZE
> > +MAX_JUMBO_FRAME_SIZE_MASK
> >
> > typedef struct CadenceGEMState {
> > /*< private >*/
> > @@ -59,6 +60,7 @@ typedef struct CadenceGEMState {
> > uint8_t num_type1_screeners;
> > uint8_t num_type2_screeners;
> > uint32_t revision;
> > + uint16_t jumbo_max_len;
> >
> > /* GEM registers backing store */
> > uint32_t regs[CADENCE_GEM_MAXREG];
> > --
> > 2.7.4
> >
- [PATCH v5 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState, (continued)
- [PATCH v5 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 12/12] net: cadence_gem: Fix RX address filtering, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 07/12] net: cadence_gem: Fix up code style, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 09/12] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 10/12] net: cadence_gem: Update the reset value for interrupt mask register, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 05/12] net: cadence_gem: Set ISR according to queue in use, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 11/12] net: cadence_gem: TX_LAST bit should be set by guest, Sai Pavan Boddu, 2020/05/12
- [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames, Sai Pavan Boddu, 2020/05/12
- Re: [PATCH v5 00/12] Cadence GEM Fixes, Jason Wang, 2020/05/14