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[PATCH 3/5] target/arm: MTE unprivileged system mode disassembly
From: |
Rémi Denis-Courmont |
Subject: |
[PATCH 3/5] target/arm: MTE unprivileged system mode disassembly |
Date: |
Fri, 13 Mar 2020 16:00:21 +0200 |
From: Rémi Denis-Courmont <address@hidden>
This adds the MTE instructions that conditionally available at EL0,
but undefined in Linux user mode.
Signed-off-by: Rémi Denis-Courmont <address@hidden>
---
target/arm/helper.c | 56 +++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 54 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ed56198623..dd64fcb4ef 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6837,6 +6837,18 @@ static const ARMCPRegInfo dcpodp_reg[] = {
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
REGINFO_SENTINEL
};
+
+static const ARMCPRegInfo mte_dcpodp_reginfo[] = {
+ { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
+ .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
+ .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
+ { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
+ .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
+ .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
+ REGINFO_SENTINEL
+};
#endif /*CONFIG_USER_ONLY*/
static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -6856,10 +6868,44 @@ static void tco_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t val)
static const ARMCPRegInfo mte_reginfo[] = {
{ .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
- .access = PL0_W, .type = ARM_CP_NOP },
+ .access = PL0_W, .type = ARM_CP_NOP,
+#ifndef CONFIG_USER_ONLY
+ .accessfn = aa64_zva_access,
+#endif
+ },
{ .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4,
- .access = PL0_W, .type = ARM_CP_DC_ZVA },
+ .access = PL0_W, .type = ARM_CP_DC_ZVA,
+#ifndef CONFIG_USER_ONLY
+ .accessfn = aa64_zva_access,
+#endif
+ },
+ { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
+ .access = PL0_W, .type = ARM_CP_NOP,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
+ .access = PL0_W, .type = ARM_CP_NOP,
+ .accessfn = aa64_cacheop_poc_access },
+#ifndef CONFIG_USER_ONLY
+ { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
+ .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
+ .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
+ { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
+ .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
+ .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
+#endif
+ { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
+ .access = PL0_W, .type = ARM_CP_NOP,
+ .accessfn = aa64_cacheop_poc_access },
+ { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
+ .access = PL0_W, .type = ARM_CP_NOP,
+ .accessfn = aa64_cacheop_poc_access },
{ .name = "TCO", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
.access = PL0_RW, .type = ARM_CP_NO_RAW,
@@ -7985,6 +8031,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
#endif /*CONFIG_USER_ONLY*/
if (cpu_isar_feature(aa64_mte, cpu)) {
define_arm_cp_regs(cpu, mte_reginfo);
+
+#ifndef CONFIG_USER_ONLY
+ if (cpu_isar_feature(aa64_dcpodp, cpu)) {
+ define_one_arm_cp_reg(cpu, mte_dcpodp_reginfo);
+ }
+#endif
}
#endif
--
2.25.1
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