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[PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DF
From: |
Peter Maydell |
Subject: |
[PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 |
Date: |
Fri, 14 Feb 2020 17:51:01 +0000 |
Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them
where we currently have hard-coded bit values.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
v1->v2: use FIELD_EX64/FIELD_DP64 for 64-bit ID register
---
target/arm/cpu.h | 10 ++++++++++
target/arm/cpu.c | 2 +-
target/arm/helper.c | 6 +++---
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ef0feb228ab..081955094dc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1821,6 +1821,16 @@ FIELD(ID_AA64MMFR2, BBM, 52, 4)
FIELD(ID_AA64MMFR2, EVT, 56, 4)
FIELD(ID_AA64MMFR2, E0PD, 60, 4)
+FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
+FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
+FIELD(ID_AA64DFR0, PMUVER, 8, 4)
+FIELD(ID_AA64DFR0, BRPS, 12, 4)
+FIELD(ID_AA64DFR0, WRPS, 20, 4)
+FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
+FIELD(ID_AA64DFR0, PMSVER, 32, 4)
+FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
+FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+
FIELD(ID_DFR0, COPDBG, 0, 4)
FIELD(ID_DFR0, COPSDBG, 4, 4)
FIELD(ID_DFR0, MMAPDBG, 8, 4)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 56f2ab865da..12bf9688007 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1718,7 +1718,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
cpu);
#endif
} else {
- cpu->id_aa64dfr0 &= ~0xf00;
+ cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER,
0);
cpu->id_dfr0 &= ~(0xf << 24);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c53d6406474..376c6412f91 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6266,9 +6266,9 @@ static void define_debug_regs(ARMCPU *cpu)
* check that if they both exist then they agree.
*/
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
- assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
- assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) == brps);
+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps);
+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) ==
ctx_cmps);
}
define_one_arm_cp_reg(cpu, &dbgdidr);
--
2.20.1
- [PATCH v2 00/21] arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2, Peter Maydell, 2020/02/14
- [PATCH v2 01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers, Peter Maydell, 2020/02/14
- [PATCH v2 02/21] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan, Peter Maydell, 2020/02/14
- [PATCH v2 04/21] target/arm: Define and use any_predinv isar_feature test, Peter Maydell, 2020/02/14
- [PATCH v2 03/21] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions, Peter Maydell, 2020/02/14
- [PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field, Peter Maydell, 2020/02/14
- [PATCH v2 05/21] target/arm: Factor out PMU register definitions, Peter Maydell, 2020/02/14
- [PATCH v2 08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function, Peter Maydell, 2020/02/14
- [PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1,
Peter Maydell <=
- [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM, Peter Maydell, 2020/02/14
- [PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks, Peter Maydell, 2020/02/14
- [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists, Peter Maydell, 2020/02/14
- [PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters, Peter Maydell, 2020/02/14
- [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension, Peter Maydell, 2020/02/14
- [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension, Peter Maydell, 2020/02/14
- [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max', Peter Maydell, 2020/02/14