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[Qemu-arm] [PATCH v2 55/68] target/arm: Convert T16, extract
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v2 55/68] target/arm: Convert T16, extract |
Date: |
Mon, 19 Aug 2019 14:37:42 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 14 +-------------
target/arm/t16.decode | 10 ++++++++++
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index cac3893386..414c562fb3 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10641,21 +10641,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
op = (insn >> 8) & 0xf;
switch (op) {
case 0: /* add/sub (sp, immediate), in decodetree */
+ case 2: /* sign/zero extend, in decodetree */
goto illegal_op;
- case 2: /* sign/zero extend. */
- ARCH(6);
- rd = insn & 7;
- rm = (insn >> 3) & 7;
- tmp = load_reg(s, rm);
- switch ((insn >> 6) & 3) {
- case 0: gen_sxth(tmp); break;
- case 1: gen_sxtb(tmp); break;
- case 2: gen_uxth(tmp); break;
- case 3: gen_uxtb(tmp); break;
- }
- store_reg(s, rd, tmp);
- break;
case 4: case 5: case 0xc: case 0xd:
/*
* 0b1011_x10x_xxxx_xxxx
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index b425b86795..b5b5086e8a 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -23,6 +23,7 @@
&s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
+&rrr_rot !extern rd rn rm rot
&ri !extern rd imm
&r !extern rm
&ldst_rr !extern p w u rn rt rm shimm shtype
@@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branchr
BLX_r 0100 0111 1 .... 000 @branchr
BXNS 0100 0111 0 .... 100 @branchr
BLXNS 0100 0111 1 .... 100 @branchr
+
+# Extend
+
+@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0
+
+SXTAH 1011 0010 00 ... ... @extend
+SXTAB 1011 0010 01 ... ... @extend
+UXTAH 1011 0010 10 ... ... @extend
+UXTAB 1011 0010 11 ... ... @extend
--
2.17.1
- [Qemu-arm] [PATCH v2 46/68] target/arm: Convert T16 load/store (register offset), (continued)
- [Qemu-arm] [PATCH v2 46/68] target/arm: Convert T16 load/store (register offset), Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 48/68] target/arm: Convert T16 add pc/sp (immediate), Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 47/68] target/arm: Convert T16 load/store (immediate offset), Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 49/68] target/arm: Convert T16 load/store multiple, Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 51/68] target/arm: Convert T16 one low register and immediate, Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 55/68] target/arm: Convert T16, extract,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 53/68] target/arm: Convert T16 add, compare, move (two high registers), Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 50/68] target/arm: Convert T16 add/sub (3 low, 2 low and imm), Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 56/68] target/arm: Convert T16, Change processor state, Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 52/68] target/arm: Convert T16 branch and exchange, Richard Henderson, 2019/08/19
- [Qemu-arm] [PATCH v2 58/68] target/arm: Convert T16, nop hints, Richard Henderson, 2019/08/19