[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH v2 26/32] target/arm: Flush tlbs for E2&0 translation
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v2 26/32] target/arm: Flush tlbs for E2&0 translation regime |
Date: |
Wed, 31 Jul 2019 13:38:07 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 31 ++++++++++++++++++++++++-------
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 30f93f4792..b9f0d387f4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3917,8 +3917,11 @@ static CPAccessResult aa64_cacheop_access(CPUARMState
*env,
static int vae1_tlbmask(CPUARMState *env)
{
+ /* Since we exclude secure first, we may read HCR_EL2 directly. */
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0;
+ } else if (env->cp15.hcr_el2 & HCR_E2H) {
+ return ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL10_0;
} else {
return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;
}
@@ -3956,6 +3959,10 @@ static int vmalle1_tlbmask(CPUARMState *env)
if (arm_is_secure_below_el3(env)) {
return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) {
+ /* Since we exclude secure first, we may read HCR_EL2 directly. */
+ if (env->cp15.hcr_el2 & HCR_E2H) {
+ return ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0;
+ }
return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_Stage2;
} else {
return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;
@@ -3971,13 +3978,22 @@ static void tlbi_aa64_alle1_write(CPUARMState *env,
const ARMCPRegInfo *ri,
tlb_flush_by_mmuidx(cs, mask);
}
+static int vae2_tlbmask(CPUARMState *env)
+{
+ if (arm_hcr_el2_eff(env) & HCR_E2H) {
+ return ARMMMUIdxBit_EL20_0 | ARMMMUIdxBit_EL20_2;
+ } else {
+ return ARMMMUIdxBit_E2;
+ }
+}
+
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = vae2_tlbmask(env);
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx(cs, mask);
}
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4002,8 +4018,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
+ int mask = vae2_tlbmask(env);
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4021,11 +4038,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env,
const ARMCPRegInfo *ri,
* Currently handles both VAE2 and VALE2, since we don't support
* flush-last-level-only.
*/
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = vae2_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.17.1
- [Qemu-arm] [PATCH v2 16/32] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, (continued)
- [Qemu-arm] [PATCH v2 16/32] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 17/32] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 19/32] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 18/32] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE*, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 20/32] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 22/32] target/arm: Add regime_has_2_ranges, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 23/32] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 21/32] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 25/32] target/arm: Install asids for E2&0 translation regime, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 24/32] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 26/32] target/arm: Flush tlbs for E2&0 translation regime,
Richard Henderson <=
- [Qemu-arm] [PATCH v2 27/32] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 31/32] target/arm: check TGE and E2H flags for EL0 pauth traps, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 30/32] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 28/32] target/arm: Update regime_is_user for EL2&0, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 29/32] target/arm: Update {fp, sve}_exception_el for VHE, Richard Henderson, 2019/07/31
- [Qemu-arm] [PATCH v2 32/32] target/arm: generate a custom MIDR for -cpu max, Richard Henderson, 2019/07/31