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Re: [Qemu-arm] [PATCH v2 00/21] aspeed: machine extensions and fixes
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH v2 00/21] aspeed: machine extensions and fixes |
Date: |
Mon, 1 Jul 2019 14:35:14 +0100 |
On Tue, 18 Jun 2019 at 17:53, Cédric Le Goater <address@hidden> wrote:
>
> Hello,
>
> This series improves the current models of the Aspeed machines in QEMU
> and adds new ones. It also prepares ground for the future Aspeed SoC.
> You will find patches for :
>
> - per SoC mappings of the memory space and the interrupt number space
> - support for multiple CPUs (improved)
> - support for multiple NICs
> - a RTC model from Joel
> - a basic XDMA model from Eddie
> - support for multiple CPUs and NICs
> - fixes for the irq and timer models from Joel, Andrew and Christian
> - DMA support for the SMC controller, which was reworked to use a RAM
> container region as suggested by Peter in September 2018
> - new swift-bmc machine from Adriana (P9' processor)
Hi; I've left review comments on some of the patches.
I'm going to take patches 1-9, 11, 12, 13, 14, 19, 20, 21
into target-arm.next (since we're nearly at softfreeze);
the others I either had comments on or they were dependent
on earlier patches in the series.
thanks
-- PMM
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