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Re: [Qemu-arm] [Qemu-devel] [PATCH v2 12/16] hw/microblaze/zynqmp: Let t
From: |
Alistair Francis |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v2 12/16] hw/microblaze/zynqmp: Let the SoC manage the IPI devices |
Date: |
Fri, 10 May 2019 13:46:55 -0700 |
On Tue, May 7, 2019 at 9:39 AM Philippe Mathieu-Daudé <address@hidden> wrote:
>
> The Inter Processor Interrupt is a block part of the SoC, not the
> "machine" (See Zynq UltraScale+ Device TRM UG1085, "Platform
> Management Unit", Power Domains and Islands).
>
> Move the IPI management from the machine to the SoC.
>
> Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> hw/microblaze/xlnx-zynqmp-pmu.c | 36 +++++++++++++++------------------
> 1 file changed, 16 insertions(+), 20 deletions(-)
>
> diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
> index eba9945c19b..20e973edf5f 100644
> --- a/hw/microblaze/xlnx-zynqmp-pmu.c
> +++ b/hw/microblaze/xlnx-zynqmp-pmu.c
> @@ -68,6 +68,13 @@ static void xlnx_zynqmp_pmu_soc_init(Object *obj)
>
> sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
> TYPE_XLNX_PMU_IO_INTC);
> +
> + /* Create the IPI device */
> + for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
> + object_initialize(&s->ipi[i], sizeof(XlnxZynqMPIPI),
> + TYPE_XLNX_ZYNQMP_IPI);
> + qdev_set_parent_bus(DEVICE(&s->ipi[i]), sysbus_get_default());
> + }
> }
>
> static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
> @@ -113,6 +120,15 @@ static void xlnx_zynqmp_pmu_soc_realize(DeviceState
> *dev, Error **errp)
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
> qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
> +
> + /* Connect the IPI device */
> + for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
> + object_property_set_bool(OBJECT(&s->ipi[i]), true, "realized",
> + &error_abort);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0,
> + qdev_get_gpio_in(DEVICE(&s->intc), ipi_irq[i]));
> + }
> }
>
> static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
> @@ -145,8 +161,6 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
> MemoryRegion *address_space_mem = get_system_memory();
> MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
> MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
> - qemu_irq irq[32];
> - int i;
>
> /* Create the ROM */
> memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
> @@ -166,24 +180,6 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
> &error_abort);
> object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
>
> - for (i = 0; i < 32; i++) {
> - irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i);
> - }
> -
> - /* Create and connect the IPI device */
> - for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
> - object_initialize(&pmu->ipi[i], sizeof(XlnxZynqMPIPI),
> - TYPE_XLNX_ZYNQMP_IPI);
> - qdev_set_parent_bus(DEVICE(&pmu->ipi[i]), sysbus_get_default());
> - }
> -
> - for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
> - object_property_set_bool(OBJECT(&pmu->ipi[i]), true, "realized",
> - &error_abort);
> - sysbus_mmio_map(SYS_BUS_DEVICE(&pmu->ipi[i]), 0, ipi_addr[i]);
> - sysbus_connect_irq(SYS_BUS_DEVICE(&pmu->ipi[i]), 0, irq[ipi_irq[i]]);
> - }
> -
> /* Load the kernel */
> microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
> machine->ram_size,
> --
> 2.20.1
>
>
- Re: [Qemu-arm] [Qemu-devel] [PATCH v2 08/16] hw/arm: Use object_initialize_child for correct reference counting, (continued)
- [Qemu-arm] [PATCH v2 09/16] hw/mips: Use object_initialize() on MIPSCPSState, Philippe Mathieu-Daudé, 2019/05/07
- [Qemu-arm] [PATCH v2 10/16] hw/mips: Use object_initialize_child for correct reference counting, Philippe Mathieu-Daudé, 2019/05/07
- [Qemu-arm] [PATCH v2 11/16] hw/microblaze/zynqmp: Move the IPI state into the PMUSoC state, Philippe Mathieu-Daudé, 2019/05/07
- [Qemu-arm] [PATCH v2 12/16] hw/microblaze/zynqmp: Let the SoC manage the IPI devices, Philippe Mathieu-Daudé, 2019/05/07
- [Qemu-arm] [PATCH v2 13/16] hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting, Philippe Mathieu-Daudé, 2019/05/07
- [Qemu-arm] [PATCH v2 14/16] hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting, Philippe Mathieu-Daudé, 2019/05/07
- [Qemu-arm] [PATCH v2 15/16] hw/arm/mps2: Use object_initialize_child for correct reference counting, Philippe Mathieu-Daudé, 2019/05/07
- [Qemu-arm] [PATCH v2 16/16] hw/intc/nvic: Use object_initialize_child for correct reference counting, Philippe Mathieu-Daudé, 2019/05/07