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[Qemu-arm] [PATCH v3 23/28] target/arm: Cache the Tagged bit for a page
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v3 23/28] target/arm: Cache the Tagged bit for a page in MemTxAttrs |
Date: |
Mon, 11 Feb 2019 15:52:53 -0800 |
This "bit" is a particular value of the page's MemAttr.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b979ca0255..e312d62140 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10740,6 +10740,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
uint64_t descaddrmask;
bool aarch64 = arm_el_is_aa64(env, el);
bool guarded = false;
+ uint8_t memattr;
/* TODO:
* This code does not handle the different format TCR for VTCR_EL2.
@@ -10970,17 +10971,21 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
txattrs->target_tlb_bit0 = true;
}
+ if (mmu_idx == ARMMMUIdx_S2NS) {
+ memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4));
+ } else {
+ /* Index into MAIR registers for cache attributes */
+ uint64_t mair = env->cp15.mair_el[el];
+ memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8);
+ }
+
+ /* When in aarch64 mode, and MTE is enabled, remember Tagged in IOTLB. */
+ if (aarch64 && memattr == 0xf0 && cpu_isar_feature(aa64_mte, cpu)) {
+ txattrs->target_tlb_bit1 = true;
+ }
+
if (cacheattrs != NULL) {
- if (mmu_idx == ARMMMUIdx_S2NS) {
- cacheattrs->attrs = convert_stage2_attrs(env,
- extract32(attrs, 0, 4));
- } else {
- /* Index into MAIR registers for cache attributes */
- uint8_t attrindx = extract32(attrs, 0, 3);
- uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
- assert(attrindx <= 7);
- cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
- }
+ cacheattrs->attrs = memattr;
cacheattrs->shareability = extract32(attrs, 6, 2);
}
--
2.17.2
- [Qemu-arm] [PATCH v3 20/28] target/arm: Implement data cache set allocation tags, (continued)
- [Qemu-arm] [PATCH v3 20/28] target/arm: Implement data cache set allocation tags, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 12/28] target/arm: Implement the GMI instruction, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 13/28] target/arm: Implement the SUBP instruction, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 07/28] target/arm: Assert no manual change to CACHED_PSTATE_BITS, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 21/28] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 16/28] target/arm: Implement the STGP instruction, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 08/28] target/arm: Add helper_mte_check{1,2}, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 19/28] target/arm: Clean address for DC ZVA, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 15/28] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 11/28] target/arm: Implement ADDG, SUBG instructions, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 23/28] target/arm: Cache the Tagged bit for a page in MemTxAttrs,
Richard Henderson <=
- [Qemu-arm] [PATCH v3 27/28] target/arm: Enable MTE, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 09/28] target/arm: Suppress tag check for sp+offset, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 28/28] tests/tcg/aarch64: Add mte smoke tests, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 24/28] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 26/28] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 25/28] target/arm: Add allocation tag storage for user mode, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 17/28] target/arm: Implement the LDGM and STGM instructions, Richard Henderson, 2019/02/11
- [Qemu-arm] [PATCH v3 22/28] tcg: Introduce target-specific page data for user-only, Richard Henderson, 2019/02/11