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[Qemu-arm] [PATCH 2/7] target/arm/translate-a64: Don't underdecode PRFM
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 2/7] target/arm/translate-a64: Don't underdecode PRFM |
Date: |
Fri, 25 Jan 2019 18:26:21 +0000 |
The PRFM prefetch insn in the load/store with imm9 encodings
requires idx field 0b00; we were underdecoding this by
only checking !is_unpriv (which is equivalent to idx != 2).
Correctly UNDEF the unallocated encodings where idx == 0b01
and 0b11 as well as 0b10.
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e6df303e321..8e081758e03 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2803,7 +2803,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t
insn,
} else {
if (size == 3 && opc == 2) {
/* PRFM - prefetch */
- if (is_unpriv) {
+ if (idx != 0) {
unallocated_encoding(s);
return;
}
--
2.20.1
- Re: [Qemu-arm] [PATCH 4/7] target/arm/translate-a64: Don't underdecode SIMD ld/st single, (continued)
- [Qemu-arm] [PATCH 1/7] target/arm/translate-a64: Don't underdecode system instructions, Peter Maydell, 2019/01/25
- [Qemu-arm] [PATCH 3/7] target/arm/translate-a64: Don't underdecode SIMD ld/st multiple, Peter Maydell, 2019/01/25
- [Qemu-arm] [PATCH 6/7] target/arm/translate-a64: Don't underdecode FP insns, Peter Maydell, 2019/01/25
- [Qemu-arm] [PATCH 5/7] target/arm/translate-a64: Don't underdecode add/sub extended register, Peter Maydell, 2019/01/25
- [Qemu-arm] [PATCH 2/7] target/arm/translate-a64: Don't underdecode PRFM,
Peter Maydell <=
- [Qemu-arm] [PATCH 7/7] target/arm/translate-a64: Don't underdecode SDOT and UDOT, Peter Maydell, 2019/01/25