[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH V6 6/6] pvpanic : update pvpanic document
From: |
Peng Hao |
Subject: |
[Qemu-arm] [PATCH V6 6/6] pvpanic : update pvpanic document |
Date: |
Mon, 12 Nov 2018 19:42:20 +0800 |
Add mmio support info in docs/specs/pvpanic.txt.
Signed-off-by: Peng Hao <address@hidden>
---
docs/specs/pvpanic.txt | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/docs/specs/pvpanic.txt b/docs/specs/pvpanic.txt
index c7bbacc..5d8e9dc 100644
--- a/docs/specs/pvpanic.txt
+++ b/docs/specs/pvpanic.txt
@@ -1,7 +1,7 @@
PVPANIC DEVICE
==============
-pvpanic device is a simulated ISA device, through which a guest panic
+pvpanic device is a simulated device, through which a guest panic
event is sent to qemu, and a QMP event is generated. This allows
management apps (e.g. libvirt) to be notified and respond to the event.
@@ -9,6 +9,10 @@ The management app has the option of waiting for
GUEST_PANICKED events,
and/or polling for guest-panicked RunState, to learn when the pvpanic
device has fired a panic event.
+When pvpanic device is implemented as a ISA device, it supports IOPORT
+mode. If pvpanic device supports MMIO mode, it will be implemented as
+a SYSBUS device.
+
ISA Interface
-------------
@@ -19,6 +23,13 @@ Software should set only bits both itself and the device
recognize.
Currently, only bit 0 is recognized, setting it indicates a guest panic
has happened.
+SYSBUS Interface
+--------------
+
+It is basically the same as ISA interface except that it uses MMIO. Pvpanic
exposes
+a address space region 0x09060000--0x09060001 in arm virt machine.
+Currently only the first byte is used.
+
ACPI Interface
--------------
--
1.8.3.1
[Qemu-arm] [PATCH V6 4/6] hw/arm/virt: Use the pvpanic device, Peng Hao, 2018/11/11
[Qemu-arm] [PATCH V6 1/6] hw/misc/pvpanic: Build the pvpanic device in $(common-obj), Peng Hao, 2018/11/11