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[Qemu-arm] [PATCH v7 06/12] target/arm: Implement PMOVSSET
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v7 06/12] target/arm: Implement PMOVSSET |
Date: |
Mon, 5 Nov 2018 18:51:56 +0000 |
Add an array for PMOVSSET so we only define it for v7ve+ platforms
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0522a606a4..6724d97346 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1342,6 +1342,13 @@ static void pmovsr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
env->cp15.c9_pmovsr &= ~value;
}
+static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ value &= pmu_counter_mask(env);
+ env->cp15.c9_pmovsr |= value;
+}
+
static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -1709,6 +1716,24 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
+ /* PMOVSSET is not implemented in v7 before v7ve */
+ { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
+ .access = PL0_RW, .accessfn = pmreg_access,
+ .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
+ .writefn = pmovsset_write,
+ .raw_writefn = raw_write },
+ { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
+ .access = PL0_RW, .accessfn = pmreg_access,
+ .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
+ .writefn = pmovsset_write,
+ .raw_writefn = raw_write },
+ REGINFO_SENTINEL
+};
+
static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -5212,6 +5237,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
!arm_feature(env, ARM_FEATURE_PMSA)) {
define_arm_cp_regs(cpu, v7mp_cp_reginfo);
}
+ if (arm_feature(env, ARM_FEATURE_V7VE)) {
+ define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
+ }
if (arm_feature(env, ARM_FEATURE_V7)) {
/* v7 performance monitor control register: same implementor
* field as main ID register, and we implement only the cycle
--
2.19.1
- [Qemu-arm] [PATCH v7 03/12] target/arm: Swap PMU values before/after migrations, (continued)
[Qemu-arm] [PATCH v7 02/12] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/11/05
[Qemu-arm] [PATCH v7 05/12] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/11/05
[Qemu-arm] [PATCH v7 04/12] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/11/05
[Qemu-arm] [PATCH v7 06/12] target/arm: Implement PMOVSSET,
Aaron Lindsay <=
[Qemu-arm] [PATCH v7 08/12] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/11/05
[Qemu-arm] [PATCH v7 07/12] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/11/05
[Qemu-arm] [PATCH v7 09/12] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/11/05
[Qemu-arm] [PATCH v7 10/12] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/11/05
[Qemu-arm] [PATCH v7 11/12] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/11/05
[Qemu-arm] [PATCH v7 12/12] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/11/05