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Re: [Qemu-arm] [Qemu-devel] [PATCH v1 10/12] target/arm: Add the Cortex-
From: |
Laurent Desnogues |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v1 10/12] target/arm: Add the Cortex-A72 |
Date: |
Tue, 9 Oct 2018 15:40:13 +0200 |
Hello,
On Tue, Oct 9, 2018 at 3:19 PM Edgar E. Iglesias
<address@hidden> wrote:
>
> Another A72 related thing I wanted to check with you. A month or two ago I was
> looking at an issue with Linux running very slowly on our models.
> Something that popped up was that Linux was running a couple of spectre
> related
> "workarounds" and "hardening" sequences on the QEMU A72s.
>
> There are a couple of bits in the ID_AARCH64_PFR0 register that
> Linux checks before enabling the sequences but I never found any
> documentation of them in the specs. Bits 56 and 60.
>
> In Linux these are refered to as:
> ID_AA64PFR0_CSV2_SHIFT
> ID_AA64PFR0_CSV3_SHIFT
>
> This is what we have in our tree:
>
> cpu->gic_vprebits = 5;
> define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
>
> /* Xilinx FIXUPs. */
> /* These indicate the BP hardening and KPTI aren't needed. */
> cpu->id_aa64pfr0 |= (uint64_t)1 << 56; /* BP. */
> cpu->id_aa64pfr0 |= (uint64_t)1 << 60; /* KPTI. */
> }
>
> Do you know what these are?
> Should we be setting these in QEMU?
These fields are publicly documented in the system register specification:
https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools
These are ARMv8.5 fields, I don't think these should be set by default
for Cortex-A72. Of course nothing prevents you from defining a
specific CPU with these fields set to boot faster :-) Or perhaps add
a property to override the default value of these registers?
Laurent
- [Qemu-arm] [PATCH v1 08/12] net: cadence_gem: Announce 64bit addressing support, (continued)
[Qemu-arm] [PATCH v1 11/12] hw/arm: versal: Add a model of Xilinx Versal SoC, Edgar E. Iglesias, 2018/10/03
[Qemu-arm] [PATCH v1 12/12] hw/arm: versal: Add a virtual Xilinx Versal board, Edgar E. Iglesias, 2018/10/03
Re: [Qemu-arm] [PATCH v1 00/12] arm: Add first models of Xilinx Versal SoC, Peter Maydell, 2018/10/08