[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH v3 7/8] xlnx-zynqmp-pmu: Connect the IPI device to the
From: |
Alistair Francis |
Subject: |
[Qemu-arm] [PATCH v3 7/8] xlnx-zynqmp-pmu: Connect the IPI device to the PMU |
Date: |
Wed, 20 Sep 2017 15:01:52 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
hw/microblaze/xlnx-zynqmp-pmu.c | 40 ++++++++++++++++++++++++++++++++++------
1 file changed, 34 insertions(+), 6 deletions(-)
diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
index ca98d82e87..2016e34db6 100644
--- a/hw/microblaze/xlnx-zynqmp-pmu.c
+++ b/hw/microblaze/xlnx-zynqmp-pmu.c
@@ -24,6 +24,7 @@
#include "cpu.h"
#include "boot.h"
+#include "hw/intc/xlnx-zynqmp-ipi.h"
#include "hw/intc/xlnx-pmu-iomod-intc.h"
/* Define the PMU device */
@@ -38,18 +39,28 @@
#define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
+#define XLNX_ZYNQMP_PMU_NUM_IPIS 4
+static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
+ 0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
+};
+static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
+ 19, 20, 21, 22,
+};
+
typedef struct XlnxZynqMPPMUState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
MicroBlazeCPU cpu;
+ XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
XlnxPMUIOIntc intc;
} XlnxZynqMPPMUState;
static void xlnx_zynqmp_pmu_init(Object *obj)
{
XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(obj);
+ int i;
object_initialize(&s->cpu, sizeof(s->cpu),
TYPE_MICROBLAZE_CPU);
@@ -58,12 +69,19 @@ static void xlnx_zynqmp_pmu_init(Object *obj)
object_initialize(&s->intc, sizeof(s->intc), TYPE_XLNX_PMU_IO_INTC);
qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default());
+
+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
+ object_initialize(&s->ipi[i], sizeof(s->ipi[i]), TYPE_XLNX_ZYNQMP_IPI);
+ qdev_set_parent_bus(DEVICE(&s->ipi[i]), sysbus_get_default());
+ }
}
static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error **errp)
{
XlnxZynqMPPMUState *s = XLNX_ZYNQMP_PMU(dev);
Error *err = NULL;
+ qemu_irq irq[32];
+ int i;
object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
"base-vectors", &error_abort);
@@ -89,12 +107,9 @@ static void xlnx_zynqmp_pmu_realize(DeviceState *dev, Error
**errp)
return;
}
- object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size",
- &error_abort);
- object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge",
- &error_abort);
- object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive",
- &error_abort);
+ object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size",
&error_abort);
+ object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge",
&error_abort);
+ object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive",
&error_abort);
object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
if (err) {
error_propagate(errp, err);
@@ -103,6 +118,19 @@ static void xlnx_zynqmp_pmu_realize(DeviceState *dev,
Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
+ for (i = 0; i < 32; i++) {
+ irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
+ }
+
+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
+ object_property_set_bool(OBJECT(&s->ipi[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0, irq[ipi_irq[i]]);
+ }
}
static void xlnx_zynqmp_pmu_class_init(ObjectClass *oc, void *data)
--
2.11.0
- [Qemu-arm] [PATCH v3 0/8] Add the ZynqMP PMU and IPI, Alistair Francis, 2017/09/20
- [Qemu-arm] [PATCH v3 1/8] xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU, Alistair Francis, 2017/09/20
- [Qemu-arm] [PATCH v3 2/8] xlnx-zynqmp-pmu: Add the CPU and memory, Alistair Francis, 2017/09/20
- [Qemu-arm] [PATCH v3 3/8] aarch64-softmmu.mak: Use an ARM specific config, Alistair Francis, 2017/09/20
- [Qemu-arm] [PATCH v3 4/8] xlnx-pmu-iomod-intc: Add the PMU Interrupt controller, Alistair Francis, 2017/09/20
- [Qemu-arm] [PATCH v3 8/8] xlnx-zynqmp: Connect the IPI device to the ZynqMP SoC, Alistair Francis, 2017/09/20
- [Qemu-arm] [PATCH v3 7/8] xlnx-zynqmp-pmu: Connect the IPI device to the PMU,
Alistair Francis <=
- [Qemu-arm] [PATCH v3 6/8] xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device, Alistair Francis, 2017/09/20