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[Qemu-arm] [PATCH v2 4/8] target-arm: Add more fields to the data abort
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-arm] [PATCH v2 4/8] target-arm: Add more fields to the data abort syndrome generator |
Date: |
Fri, 19 Feb 2016 21:04:48 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Add the following flags to the data abort syndrome generator:
* isv - Instruction syndrome valid
* sas - Syndrome access size
* sse - Syndrome sign extend
* srt - Syndrome register transfer
* sf - Sixty-Four bit register width
* ar - Acquire/Release
These flags are not yet used, so this patch has no functional change.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/internals.h | 20 ++++++++++++++++++--
target-arm/op_helper.c | 8 ++++++--
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 34e2688..4e9d9f5 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -383,13 +383,29 @@ static inline uint32_t syn_insn_abort(int same_el, int
ea, int s1ptw, int fsc)
| (ea << 9) | (s1ptw << 7) | fsc;
}
-static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
+static inline uint32_t syn_data_abort(int same_el, int isv,
+ int sas, int sse, int srt,
+ int sf, int ar,
+ int ea, int cm, int s1ptw,
int wnr, int fsc,
bool is_16bit)
{
- return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
+ uint32_t v;
+ v = (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
| (is_16bit ? 0 : ARM_EL_IL)
| (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
+
+ /* Insn Syndrome fields are RES0 if ISV is unset. */
+ if (isv) {
+ v |= (isv << 24) | (sas << 22) | (sse << 21) | (srt << 16)
+ | (sf << 15) | (ar << 14);
+ } else {
+ /* If ISV is zero, the IL field should be set to one.
+ * See ARM ARMv8 D7.2.27 for more details.
+ */
+ v |= ARM_EL_IL;
+ }
+ return v;
}
static inline uint32_t syn_swstep(int same_el, int isv, int ex)
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 7e845d5..2522d3c 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -115,7 +115,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int
is_write, int mmu_idx,
syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
exc = EXCP_PREFETCH_ABORT;
} else {
- syn = syn_data_abort(same_el, 0, 0, fi.s1ptw, is_write == 1, syn,
+ syn = syn_data_abort(same_el,
+ 0, 0, 0, 0, 0, 0,
+ 0, 0, fi.s1ptw, is_write == 1, syn,
1);
if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) {
fsr |= (1 << 11);
@@ -162,7 +164,9 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
int is_write,
}
raise_exception(env, EXCP_DATA_ABORT,
- syn_data_abort(same_el, 0, 0, 0, is_write == 1, 0x21,
+ syn_data_abort(same_el,
+ 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, is_write == 1, 0x21,
1),
target_el);
}
--
1.9.1
- [Qemu-arm] [PATCH v2 0/8] arm: Steps towards EL2 support round 6, Edgar E. Iglesias, 2016/02/19
- [Qemu-arm] [PATCH v2 1/8] tcg: Add tcg_set_insn_param, Edgar E. Iglesias, 2016/02/19
- [Qemu-arm] [PATCH v2 2/8] gen-icount: Use tcg_set_insn_param, Edgar E. Iglesias, 2016/02/19
- [Qemu-arm] [PATCH v2 3/8] target-arm: Add the IL flag to syn_data_abort, Edgar E. Iglesias, 2016/02/19
- [Qemu-arm] [PATCH v2 5/8] target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9, Edgar E. Iglesias, 2016/02/19
- [Qemu-arm] [PATCH v2 4/8] target-arm: Add more fields to the data abort syndrome generator,
Edgar E. Iglesias <=
- [Qemu-arm] [PATCH v2 6/8] target-arm/translate-a64.c: Unify some of the ldst_reg decoding, Edgar E. Iglesias, 2016/02/19
- [Qemu-arm] [PATCH v2 7/8] target-arm: A64: Create Instruction Syndromes for Data Aborts, Edgar E. Iglesias, 2016/02/19
- [Qemu-arm] [PATCH v2 8/8] target-arm: Use isyn.swstep.ex to hold the is_ldex state, Edgar E. Iglesias, 2016/02/19