@Nick No this effect I see after the GPSDO already has a lock and is running (is powered) for more than 30min.
@Andy Interesting. I agree, I also plan to use the hack, but would really like to try to find the root cause. Also, maybe I stumbled on something useful that the Ettus guys can use to improve the USRPs.
@Marcus I'm using both N200 and N210.
I just wonder that could it be that once the program is started, either in the GPSDO oscillator control loop or in the USRP motherboard clock generator a sync process is started that otherwise in standby mode is not running.
I expect that while powered the GPSDO module continuously receives the GPS signals and syncs the 10MHz reference, irrelevant of the FPGA running a program (using the 10MHz) or not . If this is so, then this effect is not related to the GPSDO. Unless, this is not true and the GPSDO is affected by the motherboard starting to use the 10 MHz reference. [Another topic, but I have also witnessed that if a signal is fed to 2 USRPs through a splitter, in the received signals I can see when the other USRP starts its program. In the one that starts before, the received signal level is reduced, once the other starts].
This leaves us the USRP motherboard clock generation circuitry that uses the GPSDO 10MHz reference to derive the 100MHz ADC clock, from where finally we get to the 10 MSps. I do not know the inner behaviour of the clock generation circuitry, but to me it seems that once a program is started in the FPGA, a certain process is started that slightly affects the ADC clock over the first 3-5 minutes. Only after this period the clock is truly stable and synced with the GPSDO. Once the program is stopped the clock is "released" from the GPSDO ref and starts to diverge again, if the program is restarted quickly, the clock is still synced well enough and we don't see the given effect, but if the pause is longer the circuitry starts syncing again and we see the effect in the delays.
If this is true. I wonder if there was a way to keep the USRP motherboard syncing the clock in the clock generation unit all the time?