I'd like to take in a 1PPS signal on the USRP1, and, using the inband FPGA firmware, trigger a reset of the timestamp on the rising edge of every 1PPS pulse to get a rough idea of timing. From reading the documentation, I know that my max input voltage cannot be higher than 3.3V, so I've got that covered, but I can't seem to get the verilog code to work. I've modified the verilog code to add the following lines to the top level code:
wire ts_io_reset; // <-- NEW LINE assign ts_io_reset = io_rx_a[0]; // <-- NEW LINE
always @ (posedge clk64 or posedge ts_io_reset) begin // <-- MODIFIED if (ts_io_reset) // <-- NEW LINE
timestamp_counter <= 32'd0; // <-- NEW LINE else if (tx_dsp_reset | rx_dsp_reset) //FIXME: does it make sense for rx/tx to reset independently?
timestamp_counter <= 32'd0; else timestamp_counter <= timestamp_counter + 32'd1; end
Nothing happens when I apply a test input to input 0 of the basic rx board (I am also polling the io from software with read_io, and I see the input switching). I am new to verilog, but for the life of me I can't figure out what I'm doing wrong here.
I am using a basic_rx and a basic_tx on side 0 of a USRP1.