Hi,
I was wonder how the RX and TX data from/to ADC is read by Altera FPGA.
I see from the schematics that FPGA and ADC take the clock from the same
output of AD9513.
From Ad9862 I read that the ADC data is latched using CLKOUT1, but this
output is not connected
to FPGA, so at which moment is the data from ADC sampled by FPGA, with
which clock?
And the same question about latching the DAC data in AD9862 send from FPGA.
I looked at the clock and it looks distorted and I wanted
to separate the ADC and FPGA clocks.
Is it possible to drive the FPGA and ADC from different clock sources? Are
different frequencies for FPGA and ADC allowed?
Do the clocks have to be synchronized? If not how much phase shift between
ADC clock and FPGA clock is allowed?
Thanks,
Przemek
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