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Re: [Discuss-gnuradio] Encoder Integration
From: |
Martin Dvh |
Subject: |
Re: [Discuss-gnuradio] Encoder Integration |
Date: |
Mon, 29 Oct 2007 00:48:45 +0100 |
User-agent: |
Icedove 1.5.0.12 (X11/20070607) |
S Mande wrote:
> Hi,
>
> I have implemented a convolutional encoder and a viterbi decoder in Verilog
> and am trying to integrate it with the existing GNU Radio software and make
> it available to everyone, once I integrate it.
>
> My encoder takes in the input binary bits and generates encoded binary bits,
> based on defined parameters.
>
> I am first focusing on integrating the encoder with the GNU Radio software.
> My understanding from the code is that the following steps are performed
> while transmitting ( i.e. benchmark_tx.py, transmit_path.py, pkt_py,
> modulation_utils.py ) :
>
> 1) Generate random bits.
> 2) Map bits to symbols (gmsk or any other modulation )
> 3) Convolve the symbols with a wave and taking discrete samples
> (Sampling)
> 4) Combine the step (3) samples with header information and make a
> packet.
> 5) Pass it on to the FPGA.
>
> Generating bits and sending it to FPGA for encoding using my encoder module
> and sending the encoded bits back to follow the above chain will possibly
> not make sense as I am overusing the bus resources, which would defeat the
> purpose of encoding in Verilog/FPGA . (bus usage should decrease by
> transmitting raw bits across the bus).
>
> So, should I pass all the above (steps 1 to 5) functionalities into the FPGA
> i.e. generate, "encode", map, convolve inside the FPGA and then pass it on
> to the existing functionalities in the FPGA ?
>
> Or is there a more optimum way to do this ?
Well you could still generate the random bits on the host.
You should however implement the other steps on the FPGA.
There are ways to implement optimized root-raised cosine filters and
(fractional) resampler filters in the FPGA if you do BPSK or QPSK.
(because you only have +1.0 and -1.0 values)
(I have some code for that if you need it)
You said you already had implemented a convolutional encoder and a viterbi
decoder in Verilog.
So it seems like combining all the parts is what has to be done.
Where exactly are you stuck.
> Any inputs on the above would help me. I am stuck with this problem for
> quite some time now.
Maybe it would help if you published what you got now somewhere, so people can
help by looking at your code.
>
> Please correct me if I am going wrong somewhere.
>
> Thanks.
>
> Best Regards,
> S. Mande.
>
>
>
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