Bdale Garbee wrote:
Aye, that's the rub. Bob's point about phase noise in the on-chip PLL
being a potential source of problem is a good one. Without digging in
to that, it suggests to me that this might be a better approach and thus
a suitable choice of VCXO is the problem we really need to address.
Yeah, phase noise is a concern. We plan to do some fairly serious phase
noise testing on the Reflock II, but it hasn't happened yet, and
probably won't in time for your event. One of the locals works for
Agilent and can get one of their latest and greatest phase noise testers
to play with, so we plan to get it and test a bunch of oscillators. The
Reflock II in various configurations (e.g., being driven by a frequency
standard as well as by 1pps) will be on the list. The HP box isn't good
enough to measure a lab frequency standard, but is plenty good for this
task. I'm also putting together a lab-style phase noise analysis system
that should be able to measure just about anything, but it's a few
months away from a maiden run.
John
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