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bug#5136: Request to update vhdl-mode and verilog-mode
From: |
Chitlesh GOORAH |
Subject: |
bug#5136: Request to update vhdl-mode and verilog-mode |
Date: |
Tue, 8 Dec 2009 18:51:15 +0100 |
Hello there,
First, I'm an emacs user since a week now. So I'm still learning the
internals. However, I've just created a patch for ghdl and fixes some
compilation warnings.
http://chitlesh.fedorapeople.org/emacs/emacs-vhdl-mode-ghdl.patch
Which seems to work for me and it can generate a proper makefile.
However I can't figure out how to tell it that if a testbench is
provided, then add the following lines to the Makefile
ghdl -m --workdir=work/ --ieee=synopsys -fexplicit $(TESTBENCH)
ghdl -r $(PROJECT)_tb --vcd=$(PROJECT).vcd --stop-time=$(STOPTIME_US)
Chitlesh
On Tue, Dec 8, 2009 at 5:37 PM, Reto Zimmermann <reto@gnu.org> wrote:
> Chitlesh GOORAH wrote:
>
>> Similarly, for vhdl-mode (included within emacs sources), weirdly does
>> not support ghdl or freehdl out of the box, but only proprietary
>> simulators. Can your vhdl-mode maintainer for emacs can fix it and put
>> ghdl as default simulator please ?
>
> Please send me the required information and I will include them.
>
> Compiler name : name used in option `vhdl-compiler' to choose compiler
> Compile command : command used for source file compilation
> Compile options : compile options (\"\\1\" inserts library name)
> Library command : command to create library directory \(\"\\1\" inserts
> library directory, \"\\2\" inserts library name)
> Library directory: directory of default library
> Error message:
> Regexp : regular expression to match error messages (*)
> File subexp index: index of subexpression that matches the file name
> Line subexp index: index of subexpression that matches the line number
> Column subexp idx: index of subexpression that matches the column number
> File message:
> Regexp : regular expression to match a file name message
> File subexp index: index of subexpression that matches the file name
> Unit-to-file name mapping: mapping of library unit names to names of files
> generated by the compiler (used for Makefile generation)
> To string : string a name is mapped to (\"\\1\" inserts the unit
> name,
> \"\\2\" inserts the entity name for architectures)
> Case adjustment : adjust case of inserted unit names
>
> Reto
>
>
bug#5136: Request to update vhdl-mode and verilog-mode, Reto Zimmermann, 2009/12/08