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qemu-riscv (thread)
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Last Modified: Mon Jan 31 2022 23:40:43 -0500
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[PATCH v5 0/6] support subsets of Float-Point in Integer Registers extensions
,
Weiwei Li
,
2022/01/28
[PATCH v5 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
Weiwei Li
,
2022/01/28
[PATCH v5 5/6] target/riscv: add support for zhinx/zhinxmin
,
Weiwei Li
,
2022/01/28
[PATCH v5 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
2022/01/28
[PATCH v5 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Weiwei Li
,
2022/01/28
[PATCH v5 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
2022/01/28
[PATCH v5 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
2022/01/28
[PATCH v7 0/5] support subsets of virtual memory extension
,
Weiwei Li
,
2022/01/28
[PATCH v7 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Weiwei Li
,
2022/01/28
Re: [PATCH v7 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Alistair Francis
,
2022/01/31
[PATCH v7 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Weiwei Li
,
2022/01/28
Re: [PATCH v7 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Alistair Francis
,
2022/01/31
[PATCH v7 3/5] target/riscv: add support for svnapot extension
,
Weiwei Li
,
2022/01/28
[PATCH v7 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2022/01/28
[PATCH v7 4/5] target/riscv: add support for svinval extension
,
Weiwei Li
,
2022/01/28
[RFC PATCH] hw/intc: Make RISC-V ACLINT mtime MMIO register writable
,
frank . chang
,
2022/01/26
Re: [RFC PATCH] hw/intc: Make RISC-V ACLINT mtime MMIO register writable
,
Alistair Francis
,
2022/01/31
[PATCH v6 0/5] support subsets of virtual memory extension
,
Weiwei Li
,
2022/01/25
[PATCH v6 3/5] target/riscv: add support for svnapot extension
,
Weiwei Li
,
2022/01/25
[PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Weiwei Li
,
2022/01/25
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
LIU Zhiwei
,
2022/01/25
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
2022/01/25
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
LIU Zhiwei
,
2022/01/25
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
2022/01/25
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Weiwei Li
,
2022/01/25
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
2022/01/27
[PATCH v6 4/5] target/riscv: add support for svinval extension
,
Weiwei Li
,
2022/01/25
[PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Weiwei Li
,
2022/01/25
Re: [PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Alistair Francis
,
2022/01/28
Re: [PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Weiwei Li
,
2022/01/28
[PATCH v6 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2022/01/25
Re: [PATCH v6 0/5] support subsets of virtual memory extension
,
Guo Ren
,
2022/01/25
[PATCH v2] target/riscv: correct "code should not be reached" for x-rv128
,
Frédéric Pétrot
,
2022/01/24
Re: [PATCH v2] target/riscv: correct "code should not be reached" for x-rv128
,
Philippe Mathieu-Daudé
,
2022/01/24
Re: [PATCH v2] target/riscv: correct "code should not be reached" for x-rv128
,
LIU Zhiwei
,
2022/01/25
Re: [PATCH v2] target/riscv: correct "code should not be reached" for x-rv128
,
Alistair Francis
,
2022/01/27
[PATCH v2] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Christoph Muellner
,
2022/01/24
Re: [PATCH v2] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Richard Henderson
,
2022/01/25
Re: [PATCH v2] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Weiwei Li
,
2022/01/26
[PATCH] target/riscv: correct "code should not be reached" for x-rv128
,
Frédéric Pétrot
,
2022/01/24
Re: [PATCH] target/riscv: correct "code should not be reached" for x-rv128
,
LIU Zhiwei
,
2022/01/24
Re: [PATCH] target/riscv: correct "code should not be reached" for x-rv128
,
Frédéric Pétrot
,
2022/01/24
Re: [PATCH] target/riscv: correct "code should not be reached" for x-rv128
,
Alistair Francis
,
2022/01/28
[PATCH 0/2] RISC-V: Correctly generate store/amo faults
,
Alistair Francis
,
2022/01/23
[PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault
,
Alistair Francis
,
2022/01/23
Re: [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault
,
LIU Zhiwei
,
2022/01/24
Re: [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault
,
Weiwei Li
,
2022/01/26
[PATCH 1/2] accel: tcg: Allow forcing a store fault on read ops
,
Alistair Francis
,
2022/01/23
Re: [PATCH 0/2] RISC-V: Correctly generate store/amo faults
,
LIU Zhiwei
,
2022/01/24
Re: [PATCH 0/2] RISC-V: Correctly generate store/amo faults
,
Richard Henderson
,
2022/01/25
Re: [PATCH 0/2] RISC-V: Correctly generate store/amo faults
,
Alistair Francis
,
2022/01/31
[PATCH v1] include: hw: remove ibex_plic.h
,
Alistair Francis
,
2022/01/21
Re: [PATCH v1] include: hw: remove ibex_plic.h
,
Alistair Francis
,
2022/01/21
Re: [PATCH v1] include: hw: remove ibex_plic.h
,
Philippe Mathieu-Daudé
,
2022/01/21
Re: [PATCH v1] include: hw: remove ibex_plic.h
,
Alistair Francis
,
2022/01/23
[RFC 0/5] Privilege version update
,
Atish Patra
,
2022/01/20
[RFC 1/5] target/riscv: Add the privileged spec version 1.12.0
,
Atish Patra
,
2022/01/20
Re: [RFC 1/5] target/riscv: Add the privileged spec version 1.12.0
,
Richard Henderson
,
2022/01/24
Re: [RFC 1/5] target/riscv: Add the privileged spec version 1.12.0
,
Atish Kumar Patra
,
2022/01/28
Re: [RFC 1/5] target/riscv: Add the privileged spec version 1.12.0
,
Alistair Francis
,
2022/01/31
[RFC 3/5] target/riscv: Add support for mconfigptr
,
Atish Patra
,
2022/01/20
[RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops.
,
Atish Patra
,
2022/01/20
Re: [RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops.
,
Richard Henderson
,
2022/01/24
Re: [RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops.
,
Atish Kumar Patra
,
2022/01/28
[RFC 4/5] target/riscv: Add *envcfg* CSRs support
,
Atish Patra
,
2022/01/20
Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support
,
Weiwei Li
,
2022/01/26
Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support
,
Atish Patra
,
2022/01/28
Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support
,
angell1518
,
2022/01/28
Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support
,
Atish Kumar Patra
,
2022/01/31
[RFC 5/5] target/riscv: Enable privileged spec version 1.12
,
Atish Patra
,
2022/01/20
Re: [RFC 5/5] target/riscv: Enable privileged spec version 1.12
,
Christoph Müllner
,
2022/01/24
[PATCH v8 00/23] Support UXL filed in xstatus
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 02/23] target/riscv: Don't save pc when exception return
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 05/23] target/riscv: Create xl field in env
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 07/23] target/riscv: Extend pc for runtime pc write
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 09/23] target/riscv: Relax debug check for pm write
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base]
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 11/23] target/riscv: Create current pm fields in env
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 13/23] target/riscv: Calculate address according to XLEN
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 15/23] target/riscv: Split out the vill from vtype
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 18/23] target/riscv: Fix check range for first fault only
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 19/23] target/riscv: Adjust vector address with mask
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 22/23] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
2022/01/20
[PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor
,
LIU Zhiwei
,
2022/01/20
Re: [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor
,
Alistair Francis
,
2022/01/20
[PATCH v8 23/23] target/riscv: Relax UXL field for debugging
,
LIU Zhiwei
,
2022/01/20
Re: [PATCH v8 00/23] Support UXL filed in xstatus
,
Alistair Francis
,
2022/01/20
[PATCH v3 0/3] Improve RISC-V spike machine bios support
,
Anup Patel
,
2022/01/20
[PATCH v3 1/3] hw/riscv: spike: Allow using binary firmware as bios
,
Anup Patel
,
2022/01/20
[PATCH v3 2/3] hw/riscv: Remove macros for ELF BIOS image names
,
Anup Patel
,
2022/01/20
[PATCH v3 3/3] roms/opensbi: Remove ELF images
,
Anup Patel
,
2022/01/20
Re: [PATCH v3 0/3] Improve RISC-V spike machine bios support
,
Alistair Francis
,
2022/01/20
[PATCH v8 00/23] QEMU RISC-V AIA support
,
Anup Patel
,
2022/01/19
[PATCH v8 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
,
Anup Patel
,
2022/01/19
[PATCH v8 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs
,
Anup Patel
,
2022/01/19
[PATCH v8 03/23] target/riscv: Implement hgeie and hgeip CSRs
,
Anup Patel
,
2022/01/19
[PATCH v8 04/23] target/riscv: Improve delivery of guest external interrupts
,
Anup Patel
,
2022/01/19
[PATCH v8 05/23] target/riscv: Allow setting CPU feature from machine/device emulation
,
Anup Patel
,
2022/01/19
[PATCH v8 06/23] target/riscv: Add AIA cpu feature
,
Anup Patel
,
2022/01/19
[PATCH v8 07/23] target/riscv: Add defines for AIA CSRs
,
Anup Patel
,
2022/01/19
[PATCH v8 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Anup Patel
,
2022/01/19
[PATCH v8 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
2022/01/19
Re: [PATCH v8 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
2022/01/20
[PATCH v8 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Anup Patel
,
2022/01/19
[PATCH v8 12/23] target/riscv: Implement AIA interrupt filtering CSRs
,
Anup Patel
,
2022/01/19
[PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
,
Anup Patel
,
2022/01/19
Re: [PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
,
Alistair Francis
,
2022/01/20
[PATCH v8 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
2022/01/19
[PATCH v8 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
2022/01/19
Re: [PATCH v8 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Alistair Francis
,
2022/01/20
[PATCH v8 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Anup Patel
,
2022/01/19
[PATCH v8 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
,
Anup Patel
,
2022/01/19
[PATCH v8 17/23] target/riscv: Allow users to force enable AIA CSRs in HART
,
Anup Patel
,
2022/01/19
[PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
2022/01/19
Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
2022/01/19
Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
2022/01/19
Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
2022/01/20
Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
2022/01/20
Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
2022/01/20
[PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
,
Anup Patel
,
2022/01/19
Re: [PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
,
Alistair Francis
,
2022/01/24
[PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
2022/01/19
Re: [PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Alistair Francis
,
2022/01/27
Re: [PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
2022/01/27
[PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
,
Anup Patel
,
2022/01/19
Re: [PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
,
Alistair Francis
,
2022/01/27
[PATCH v8 22/23] docs/system: riscv: Document AIA options for virt machine
,
Anup Patel
,
2022/01/19
[PATCH v8 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
,
Anup Patel
,
2022/01/19
Re: [PATCH v8 00/23] QEMU RISC-V AIA support
,
Anup Patel
,
2022/01/20
Re: [PATCH v8 00/23] QEMU RISC-V AIA support
,
Alistair Francis
,
2022/01/21
[RFC PATCH v5 00/14] support subsets of scalar crypto extension
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 03/14] target/riscv: rvk: add support for zbkc extension
,
Weiwei Li
,
2022/01/19
Re: [RFC PATCH v5 03/14] target/riscv: rvk: add support for zbkc extension
,
Alistair Francis
,
2022/01/20
[RFC PATCH v5 02/14] target/riscv: rvk: add support for zbkb extension
,
Weiwei Li
,
2022/01/19
Re: [RFC PATCH v5 02/14] target/riscv: rvk: add support for zbkb extension
,
Alistair Francis
,
2022/01/20
[RFC PATCH v5 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 04/14] target/riscv: rvk: add support for zbkx extension
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 05/14] crypto: move sm4_sbox from target/arm
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 11/14] target/riscv: rvk: add support for zksed/zksh extension
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
,
Weiwei Li
,
2022/01/19
[RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
2022/01/19
Re: [RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties
,
Alistair Francis
,
2022/01/20
Re: [RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
2022/01/21
[RFC PATCH v5 12/14] target/riscv: rvk: add CSR support for Zkr
,
Weiwei Li
,
2022/01/19
[PATCH v7 00/22] Support UXL filed in xstatus
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 02/22] target/riscv: Don't save pc when exception return
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 03/22] target/riscv: Sign extend link reg for jal and jalr
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 04/22] target/riscv: Sign extend pc for different XLEN
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 05/22] target/riscv: Create xl field in env
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 06/22] target/riscv: Ignore the pc bits above XLEN
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 07/22] target/riscv: Extend pc for runtime pc write
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 08/22] target/riscv: Use gdb xml according to max mxlen
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 09/22] target/riscv: Relax debug check for pm write
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 10/22] target/riscv: Adjust csr write mask with XLEN
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 11/22] target/riscv: Create current pm fields in env
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base]
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 13/22] target/riscv: Calculate address according to XLEN
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 15/22] target/riscv: Split out the vill from vtype
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 18/22] target/riscv: Fix check range for first fault only
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 19/22] target/riscv: Adjust vector address with mask
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 21/22] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
2022/01/19
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
,
Alistair Francis
,
2022/01/19
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
2022/01/19
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
,
Alistair Francis
,
2022/01/19
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
2022/01/20
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
2022/01/19
[PATCH v7 22/22] target/riscv: Relax UXL field for debugging
,
LIU Zhiwei
,
2022/01/19
[RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Christoph Muellner
,
2022/01/18
Re: [RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Atish Patra
,
2022/01/18
Re: [RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Christoph Müllner
,
2022/01/21
Re: [RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Atish Patra
,
2022/01/21
[RESEND] target/riscv: fix RV128 lq encoding
,
Christoph Muellner
,
2022/01/18
Re: [RESEND] target/riscv: fix RV128 lq encoding
,
Frédéric Pétrot
,
2022/01/19
Re: [RESEND] target/riscv: fix RV128 lq encoding
,
Christoph Müllner
,
2022/01/20
Re: [RESEND] target/riscv: fix RV128 lq encoding
,
Philipp Tomsich
,
2022/01/19
[PATCH] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Christoph Muellner
,
2022/01/18
Re: [PATCH] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Christoph Müllner
,
2022/01/18
[PATCH] target/riscv: fix RV128 lq encoding
,
Christoph Muellner
,
2022/01/18
Re: [PATCH] target/riscv: fix RV128 lq encoding
,
Christoph Müllner
,
2022/01/18
[PATCH v2 0/3] Improve RISC-V spike machine bios support
,
Anup Patel
,
2022/01/18
[PATCH v2 1/3] hw/riscv: spike: Allow using binary firmware as bios
,
Anup Patel
,
2022/01/18
Re: [PATCH v2 1/3] hw/riscv: spike: Allow using binary firmware as bios
,
Alistair Francis
,
2022/01/18
Re: [PATCH v2 1/3] hw/riscv: spike: Allow using binary firmware as bios
,
Bin Meng
,
2022/01/19
[PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names
,
Anup Patel
,
2022/01/18
Re: [PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names
,
Alistair Francis
,
2022/01/18
Re: [PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names
,
Bin Meng
,
2022/01/19
[PATCH v2 3/3] roms/opensbi: Remove ELF images
,
Anup Patel
,
2022/01/18
Re: [PATCH v2 3/3] roms/opensbi: Remove ELF images
,
Alistair Francis
,
2022/01/18
Re: [PATCH v2 3/3] roms/opensbi: Remove ELF images
,
Bin Meng
,
2022/01/19
Re: [PATCH v2 3/3] roms/opensbi: Remove ELF images
,
Anup Patel
,
2022/01/20
[PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions
,
frank . chang
,
2022/01/17
[PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns
,
frank . chang
,
2022/01/17
[PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
,
frank . chang
,
2022/01/17
[PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
,
frank . chang
,
2022/01/17
Re: [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
,
Alistair Francis
,
2022/01/17
[PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
,
frank . chang
,
2022/01/17
[PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
,
frank . chang
,
2022/01/17
[PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
,
frank . chang
,
2022/01/17
[PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
,
frank . chang
,
2022/01/17
[PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
,
frank . chang
,
2022/01/17
[PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
,
frank . chang
,
2022/01/17
[PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
,
frank . chang
,
2022/01/17
[PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
,
frank . chang
,
2022/01/17
[PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns
,
frank . chang
,
2022/01/17
[PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
,
frank . chang
,
2022/01/17
[PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
,
frank . chang
,
2022/01/17
[PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
,
frank . chang
,
2022/01/17
[PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
,
frank . chang
,
2022/01/17
[PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
,
frank . chang
,
2022/01/17
Re: [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions
,
Alistair Francis
,
2022/01/18
[PATCH v5 0/5] support subsets of virtual memory extension
,
Weiwei Li
,
2022/01/17
[PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Weiwei Li
,
2022/01/17
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Anup Patel
,
2022/01/17
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Alistair Francis
,
2022/01/17
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
2022/01/18
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
2022/01/20
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
LIU Zhiwei
,
2022/01/20
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
2022/01/20
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
LIU Zhiwei
,
2022/01/20
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
2022/01/18
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Anup Patel
,
2022/01/18
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
2022/01/18
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Anup Patel
,
2022/01/18
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Anup Patel
,
2022/01/18
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
2022/01/18
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Weiwei Li
,
2022/01/18
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
LIU Zhiwei
,
2022/01/18
[PATCH v5 3/5] target/riscv: add support for svnapot extension
,
Weiwei Li
,
2022/01/17
Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension
,
Anup Patel
,
2022/01/17
Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension
,
Weiwei Li
,
2022/01/18
[PATCH v5 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Weiwei Li
,
2022/01/17
[PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2022/01/17
Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Anup Patel
,
2022/01/17
Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2022/01/18
Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2022/01/18
Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Anup Patel
,
2022/01/18
Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2022/01/18
[PATCH v5 4/5] target/riscv: add support for svinval extension
,
Weiwei Li
,
2022/01/17
Re: [PATCH 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
,
Alistair Francis
,
2022/01/17
Re: [PATCH 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
,
Alistair Francis
,
2022/01/17
Re: [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
,
Alistair Francis
,
2022/01/17
Re: [PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
,
Alistair Francis
,
2022/01/17
Re: [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
,
Frank Chang
,
2022/01/17
Re: [PATCH 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
,
Alistair Francis
,
2022/01/17
Re: [PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns
,
Alistair Francis
,
2022/01/17
[PATCH v7 00/23] QEMU RISC-V AIA support
,
Anup Patel
,
2022/01/17
[PATCH v7 03/23] target/riscv: Implement hgeie and hgeip CSRs
,
Anup Patel
,
2022/01/17
[PATCH v7 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs
,
Anup Patel
,
2022/01/17
[PATCH v7 04/23] target/riscv: Improve delivery of guest external interrupts
,
Anup Patel
,
2022/01/17
[PATCH v7 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
,
Anup Patel
,
2022/01/17
[PATCH v7 12/23] target/riscv: Implement AIA interrupt filtering CSRs
,
Anup Patel
,
2022/01/17
[PATCH v7 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
2022/01/17
[PATCH v7 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
2022/01/17
[PATCH v7 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Anup Patel
,
2022/01/17
[PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Anup Patel
,
2022/01/17
Re: [PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Frank Chang
,
2022/01/17
[PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
2022/01/17
Re: [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
2022/01/17
Re: [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
2022/01/17
Re: [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
2022/01/17
[PATCH v7 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
,
Anup Patel
,
2022/01/17
[PATCH v7 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Anup Patel
,
2022/01/17
[PATCH v7 07/23] target/riscv: Add defines for AIA CSRs
,
Anup Patel
,
2022/01/17
[PATCH v7 17/23] target/riscv: Allow users to force enable AIA CSRs in HART
,
Anup Patel
,
2022/01/17
[PATCH v7 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
,
Anup Patel
,
2022/01/17
[PATCH v7 05/23] target/riscv: Allow setting CPU feature from machine/device emulation
,
Anup Patel
,
2022/01/17
[PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
2022/01/17
Re: [PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
2022/01/18
[PATCH v7 22/23] docs/system: riscv: Document AIA options for virt machine
,
Anup Patel
,
2022/01/17
[PATCH v7 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
,
Anup Patel
,
2022/01/17
[PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
,
Anup Patel
,
2022/01/17
[PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
2022/01/17
Re: [PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Frank Chang
,
2022/01/17
[PATCH v7 06/23] target/riscv: Add AIA cpu feature
,
Anup Patel
,
2022/01/17
[PATCH v7 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
,
Anup Patel
,
2022/01/17
Re: [PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions
,
Frank Chang
,
2022/01/17
[PATCH] target/riscv: Ignore reserved bits in PTE for RV64
,
guoren
,
2022/01/17
Re: [PATCH] target/riscv: Ignore reserved bits in PTE for RV64
,
Alistair Francis
,
2022/01/17
[PATCH v4 0/4] support subsets of virtual memory extension
,
Weiwei Li
,
2022/01/15
[PATCH v4 4/4] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2022/01/15
Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension
,
Guo Ren
,
2022/01/17
Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2022/01/17
[PATCH v4 3/4] target/riscv: add support for svinval extension
,
Weiwei Li
,
2022/01/15
[PATCH v4 2/4] target/riscv: add support for svnapot extension
,
Weiwei Li
,
2022/01/15
Re: [PATCH v4 2/4] target/riscv: add support for svnapot extension
,
Anup Patel
,
2022/01/15
[PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Weiwei Li
,
2022/01/15
[PATCH] hw/riscv: spike: Allow using binary firmware as bios
,
Anup Patel
,
2022/01/14
Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios
,
Alistair Francis
,
2022/01/18
Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios
,
Anup Patel
,
2022/01/18
Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios
,
Alistair Francis
,
2022/01/18
Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios
,
Anup Patel
,
2022/01/18
Re: [PATCH v6 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Frank Chang
,
2022/01/14
Re: [PATCH v6 03/23] target/riscv: Implement hgeie and hgeip CSRs
,
Frank Chang
,
2022/01/14
[PATCH v3 0/3] support subsets of virtual memory extension
,
Weiwei Li
,
2022/01/13
[PATCH v3 1/3] target/riscv: add support for svnapot extension
,
Weiwei Li
,
2022/01/13
[PATCH v3 3/3] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2022/01/13
Re: [PATCH v3 3/3] target/riscv: add support for svpbmt extension
,
Anup Patel
,
2022/01/14
Re: [PATCH v3 3/3] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
2022/01/14
[PATCH v3 2/3] target/riscv: add support for svinval extension
,
Weiwei Li
,
2022/01/13
Re: [PATCH v3 2/3] target/riscv: add support for svinval extension
,
Anup Patel
,
2022/01/14
Re: [PATCH v3 2/3] target/riscv: add support for svinval extension
,
Weiwei Li
,
2022/01/14
Re: [PATCH v3 2/3] target/riscv: add support for svinval extension
,
Anup Patel
,
2022/01/14
Re: [PATCH v3 2/3] target/riscv: add support for svinval extension
,
Weiwei Li
,
2022/01/14
[PATCH v2 1/2] target/riscv: iterate over a table of decoders
,
Philipp Tomsich
,
2022/01/13
[PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philipp Tomsich
,
2022/01/13
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Alistair Francis
,
2022/01/18
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philipp Tomsich
,
2022/01/18
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Alistair Francis
,
2022/01/18
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Alistair Francis
,
2022/01/18
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philipp Tomsich
,
2022/01/20
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Alistair Francis
,
2022/01/20
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philippe Mathieu-Daudé
,
2022/01/19
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philipp Tomsich
,
2022/01/20
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Richard Henderson
,
2022/01/25
Re: [PATCH v2 1/2] target/riscv: iterate over a table of decoders
,
Philippe Mathieu-Daudé
,
2022/01/19
Re: [PATCH v2 1/2] target/riscv: iterate over a table of decoders
,
Philipp Tomsich
,
2022/01/20
Re: [PATCH v2 1/2] target/riscv: iterate over a table of decoders
,
Richard Henderson
,
2022/01/25
Re: [PATCH v6 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs
,
Frank Chang
,
2022/01/13
[PATCH v6 00/22] Support UXL filed in xstatus
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 01/22] target/riscv: Adjust pmpcfg access with mxl
,
LIU Zhiwei
,
2022/01/13
Re: [PATCH v6 01/22] target/riscv: Adjust pmpcfg access with mxl
,
Alistair Francis
,
2022/01/18
[PATCH v6 02/22] target/riscv: Don't save pc when exception return
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr
,
LIU Zhiwei
,
2022/01/13
Re: [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr
,
Alistair Francis
,
2022/01/18
[PATCH v6 04/22] target/riscv: Sign extend pc for different XLEN
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 05/22] target/riscv: Create xl field in env
,
LIU Zhiwei
,
2022/01/13
Re: [PATCH v6 05/22] target/riscv: Create xl field in env
,
Alistair Francis
,
2022/01/18
Re: [PATCH v6 05/22] target/riscv: Create xl field in env
,
LIU Zhiwei
,
2022/01/18
Re: [PATCH v6 05/22] target/riscv: Create xl field in env
,
Alistair Francis
,
2022/01/18
[PATCH v6 06/22] target/riscv: Ignore the pc bits above XLEN
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 07/22] target/riscv: Extend pc for runtime pc write
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 08/22] target/riscv: Use gdb xml according to max mxlen
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 09/22] target/riscv: Relax debug check for pm write
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 11/22] target/riscv: Create current pm fields in env
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base]
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 13/22] target/riscv: Calculate address according to XLEN
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 15/22] target/riscv: Split out the vill from vtype
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 18/22] target/riscv: Fix check range for first fault only
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 19/22] target/riscv: Adjust vector address with mask
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN
,
LIU Zhiwei
,
2022/01/13
Re: [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN
,
Alistair Francis
,
2022/01/18
[PATCH v6 21/22] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
2022/01/13
[PATCH v6 22/22] target/riscv: Relax UXL field for debugging
,
LIU Zhiwei
,
2022/01/13
Re: [PATCH v6 22/22] target/riscv: Relax UXL field for debugging
,
Alistair Francis
,
2022/01/18
Re: [PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts
,
Frank Chang
,
2022/01/13
Re: [PATCH v6 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Frank Chang
,
2022/01/13
Re: [PATCH v6 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
2022/01/13
[PATCH v4 0/6] support subsets of Float-Point in Integer Registers extensions
,
Weiwei Li
,
2022/01/12
[PATCH v4 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
2022/01/12
Re: [PATCH v4 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Alistair Francis
,
2022/01/28
[PATCH v4 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
2022/01/12
Re: [PATCH v4 3/6] target/riscv: add support for zfinx
,
Alistair Francis
,
2022/01/28
Re: [PATCH v4 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
2022/01/28
[PATCH v4 5/6] target/riscv: add support for zhinx/zhinxmin
,
Weiwei Li
,
2022/01/12
[PATCH v4 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Weiwei Li
,
2022/01/12
Re: [PATCH v4 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Alistair Francis
,
2022/01/28
[PATCH v4 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
Weiwei Li
,
2022/01/12
Re: [PATCH v4 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
Alistair Francis
,
2022/01/28
[PATCH v4 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
2022/01/12
Re: [PATCH v6 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 22/23] docs/system: riscv: Document AIA options for virt machine
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 17/23] target/riscv: Allow users to force enable AIA CSRs in HART
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
2022/01/13
Re: [PATCH v6 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 07/23] target/riscv: Add defines for AIA CSRs
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 06/23] target/riscv: Add AIA cpu feature
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/device emulation
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Frank Chang
,
2022/01/12
Re: [PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
2022/01/13
[PATCH v5 00/13] Add riscv kvm accel support
,
Yifei Jiang
,
2022/01/12
[PATCH v5 01/13] update-linux-headers: Add asm-riscv/kvm.h
,
Yifei Jiang
,
2022/01/12
[PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Yifei Jiang
,
2022/01/12
[PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu
,
Yifei Jiang
,
2022/01/12
[PATCH v5 04/13] target/riscv: Implement kvm_arch_get_registers
,
Yifei Jiang
,
2022/01/12
[PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers
,
Yifei Jiang
,
2022/01/12
[PATCH v5 06/13] target/riscv: Support start kernel directly by KVM
,
Yifei Jiang
,
2022/01/12
Re: [PATCH v5 06/13] target/riscv: Support start kernel directly by KVM
,
Anup Patel
,
2022/01/12
[PATCH v5 07/13] target/riscv: Support setting external interrupt by KVM
,
Yifei Jiang
,
2022/01/12
[PATCH v5 08/13] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Yifei Jiang
,
2022/01/12
[PATCH v5 09/13] target/riscv: Add host cpu type
,
Yifei Jiang
,
2022/01/12
[PATCH v5 10/13] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Yifei Jiang
,
2022/01/12
[PATCH v5 11/13] target/riscv: Implement virtual time adjusting with vm state changing
,
Yifei Jiang
,
2022/01/12
[PATCH v5 12/13] target/riscv: Support virtual time context synchronization
,
Yifei Jiang
,
2022/01/12
[PATCH v5 13/13] target/riscv: enable riscv kvm accel
,
Yifei Jiang
,
2022/01/12
Re: [PATCH v5 13/13] target/riscv: enable riscv kvm accel
,
Alistair Francis
,
2022/01/12
Re: [PATCH v5 13/13] target/riscv: enable riscv kvm accel
,
Anup Patel
,
2022/01/12
Re: [PATCH v5 00/13] Add riscv kvm accel support
,
Alistair Francis
,
2022/01/17
[PATCH v2 1/2] riscv: opentitan: fixup plic stride len
,
Alistair Francis
,
2022/01/11
[PATCH v2 2/2] hw: timer: ibex_timer: update/add reg address
,
Alistair Francis
,
2022/01/11
Re: [PATCH v6 12/23] target/riscv: Implement AIA interrupt filtering CSRs
,
Frank Chang
,
2022/01/11
[PATCH v4 0/7] support subsets of scalar crypto extension
,
Weiwei Li
,
2022/01/10
[PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
2022/01/10
Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
Alistair Francis
,
2022/01/17
Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
2022/01/18
[PATCH v4 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*
,
Weiwei Li
,
2022/01/10
[PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
,
Weiwei Li
,
2022/01/10
Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
,
Alistair Francis
,
2022/01/17
Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
,
Weiwei Li
,
2022/01/17
[PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
,
Weiwei Li
,
2022/01/10
Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
,
Alistair Francis
,
2022/01/17
Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
,
Weiwei Li
,
2022/01/18
[PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
,
Weiwei Li
,
2022/01/10
Re: [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
,
Alistair Francis
,
2022/01/17
Re: [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
,
Weiwei Li
,
2022/01/18
[PATCH v4 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
,
Weiwei Li
,
2022/01/10
[PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
,
Weiwei Li
,
2022/01/10
Re: [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
,
Alistair Francis
,
2022/01/17
Re: [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
,
Weiwei Li
,
2022/01/18
Re: [PATCH v4 0/7] support subsets of scalar crypto extension
,
Alistair Francis
,
2022/01/17
Re: [PATCH v4 0/7] support subsets of scalar crypto extension
,
Weiwei Li
,
2022/01/18
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
2022/01/10
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
2022/01/11
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
2022/01/11
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
2022/01/13
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
2022/01/13
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
2022/01/10
Re: [PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
Alistair Francis
,
2022/01/10
Re: [PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
2022/01/10
[PATCH 1/2] riscv: opentitan: fixup plic stride len
,
Alistair Francis
,
2022/01/10
[PATCH 2/2] hw: timer: ibex_timer: update/add reg address
,
Alistair Francis
,
2022/01/10
Re: [PATCH 2/2] hw: timer: ibex_timer: update/add reg address
,
Alistair Francis
,
2022/01/10
Re: [PATCH 2/2] hw: timer: ibex_timer: update/add reg address
,
Bin Meng
,
2022/01/10
Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
,
Alistair Francis
,
2022/01/10
Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
,
Bin Meng
,
2022/01/10
Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
,
Wilfred Mallawa
,
2022/01/10
[PATCH] hw: timer: ibex_timer: Fixup reading w/o register
,
Alistair Francis
,
2022/01/10
Re: [PATCH] hw: timer: ibex_timer: Fixup reading w/o register
,
Bin Meng
,
2022/01/10
Re: [PATCH] hw: timer: ibex_timer: Fixup reading w/o register
,
Alistair Francis
,
2022/01/10
Re: [PATCH] hw: timer: ibex_timer: Fixup reading w/o register
,
Philippe Mathieu-Daudé
,
2022/01/10
Re: [PATCH] hw: timer: ibex_timer: Fixup reading w/o register
,
Alistair Francis
,
2022/01/10
[PATCH v4 00/12] Add riscv kvm accel support
,
Yifei Jiang
,
2022/01/09
[PATCH v4 01/12] update-linux-headers: Add asm-riscv/kvm.h
,
Yifei Jiang
,
2022/01/09
[PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Yifei Jiang
,
2022/01/09
Re: [PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Alistair Francis
,
2022/01/10
RE: [PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Jiangyifei
,
2022/01/12
[PATCH v4 03/12] target/riscv: Implement function kvm_arch_init_vcpu
,
Yifei Jiang
,
2022/01/09
[PATCH v4 06/12] target/riscv: Support start kernel directly by KVM
,
Yifei Jiang
,
2022/01/09
Re: [PATCH v4 06/12] target/riscv: Support start kernel directly by KVM
,
Alistair Francis
,
2022/01/10
RE: [PATCH v4 06/12] target/riscv: Support start kernel directly by KVM
,
Jiangyifei
,
2022/01/12
[PATCH v4 07/12] target/riscv: Support setting external interrupt by KVM
,
Yifei Jiang
,
2022/01/09
[PATCH v4 04/12] target/riscv: Implement kvm_arch_get_registers
,
Yifei Jiang
,
2022/01/09
[PATCH v4 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Yifei Jiang
,
2022/01/09
Re: [PATCH v4 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Alistair Francis
,
2022/01/10
[PATCH v4 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Yifei Jiang
,
2022/01/09
Re: [PATCH v4 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Alistair Francis
,
2022/01/10
[PATCH v4 12/12] target/riscv: Support virtual time context synchronization
,
Yifei Jiang
,
2022/01/09
[PATCH v4 11/12] target/riscv: Implement virtual time adjusting with vm state changing
,
Yifei Jiang
,
2022/01/09
[PATCH v4 09/12] target/riscv: Add host cpu type
,
Yifei Jiang
,
2022/01/09
[PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers
,
Yifei Jiang
,
2022/01/09
Re: [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers
,
Alistair Francis
,
2022/01/10
RE: [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers
,
Jiangyifei
,
2022/01/12
RE: [PATCH v3 06/12] target/riscv: Support start kernel directly by KVM
,
Jiangyifei
,
2022/01/09
[PATCH v1 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philipp Tomsich
,
2022/01/09
[PATCH v3 0/6] support subsets of Float-Point in Integer Registers extensions
,
Weiwei Li
,
2022/01/07
[PATCH v3 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
2022/01/07
Re: [PATCH v3 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Richard Henderson
,
2022/01/07
Re: [PATCH v3 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
2022/01/07
[PATCH v3 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
Weiwei Li
,
2022/01/07
[PATCH v3 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
2022/01/07
Re: [PATCH v3 4/6] target/riscv: add support for zdinx
,
Richard Henderson
,
2022/01/07
Re: [PATCH v3 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
2022/01/07
[PATCH v3 5/6] target/riscv: add support for zhinx/zhinxmin
,
Weiwei Li
,
2022/01/07
[PATCH v3 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
2022/01/07
[PATCH v3 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Weiwei Li
,
2022/01/07
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
2022/01/07
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
2022/01/08
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
2022/01/08
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
2022/01/08
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
2022/01/14
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
2022/01/14
Re: [PATCH v4 0/3] RISC-V: Populate mtval and stval
,
Alistair Francis
,
2022/01/06
[PATCH v4 00/11] Improve PMU support
,
Atish Patra
,
2022/01/06
[PATCH v4 10/11] target/riscv: Add few cache related PMU events
,
Atish Patra
,
2022/01/06
[PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
2022/01/06
Re: [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree
,
Philippe Mathieu-Daudé
,
2022/01/07
Re: [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
2022/01/09
Re: [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree
,
Bin Meng
,
2022/01/10
Re: [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Kumar Patra
,
2022/01/10
[PATCH v4 05/11] target/riscv: Implement mcountinhibit CSR
,
Atish Patra
,
2022/01/06
[PATCH v4 06/11] target/riscv: Add support for hpmcounters/hpmevents
,
Atish Patra
,
2022/01/06
Re: [PATCH v4 06/11] target/riscv: Add support for hpmcounters/hpmevents
,
Bin Meng
,
2022/01/07
[PATCH v4 03/11] target/riscv: pmu: Rename the counters extension to pmu
,
Atish Patra
,
2022/01/06
[PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
2022/01/06
Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation
,
Bin Meng
,
2022/01/10
Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
2022/01/11
Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation
,
Bin Meng
,
2022/01/12
[PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function
,
Atish Patra
,
2022/01/06
[PATCH v4 08/11] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
2022/01/06
Re: [PATCH v4 08/11] target/riscv: Add sscofpmf extension support
,
Anup Patel
,
2022/01/10
Re: [PATCH v4 08/11] target/riscv: Add sscofpmf extension support
,
Atish Kumar Patra
,
2022/01/10
[PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode
,
Atish Patra
,
2022/01/06
Re: [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode
,
Bin Meng
,
2022/01/07
[PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
2022/01/06
Re: [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable
,
Bin Meng
,
2022/01/07
Re: [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable
,
Alistair Francis
,
2022/01/10
[PATCH v4 09/11] target/riscv: Simplify counter predicate function
,
Atish Patra
,
2022/01/06
Re: [PATCH v4 09/11] target/riscv: Simplify counter predicate function
,
Bin Meng
,
2022/01/10
Re: [PATCH v4 09/11] target/riscv: Simplify counter predicate function
,
Atish Kumar Patra
,
2022/01/10
Re: [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
2022/01/06
[PATCH v8 00/18] Adding partial support for 128-bit riscv target
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 02/18] exec/memop: Adding signed quad and octo defines
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 01/18] exec/memop: Adding signedness to quad definitions
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 04/18] target/riscv: additional macros to check instruction support
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 06/18] target/riscv: array for the 64 upper bits of 128-bit registers
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 03/18] qemu/int128: addition of div/rem 128-bit operations
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 05/18] target/riscv: separation of bitwise logic and arithmetic helpers
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 08/18] target/riscv: moving some insns close to similar insns
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 09/18] target/riscv: accessors to registers upper part and 128-bit load/store
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Frédéric Pétrot
,
2022/01/06
Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Alistair Francis
,
2022/01/06
Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Frédéric Pétrot
,
2022/01/07
Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Alistair Francis
,
2022/01/07
Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Frédéric Pétrot
,
2022/01/07
[PATCH v8 10/18] target/riscv: support for 128-bit bitwise instructions
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 15/18] target/riscv: adding high part of some csrs
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 14/18] target/riscv: support for 128-bit M extension
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 11/18] target/riscv: support for 128-bit U-type instructions
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 12/18] target/riscv: support for 128-bit shift instructions
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 13/18] target/riscv: support for 128-bit arithmetic instructions
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 18/18] target/riscv: actual functions to realize crs 128-bit insns
,
Frédéric Pétrot
,
2022/01/06
[PATCH v8 17/18] target/riscv: modification of the trans_csrxx for 128-bit support
,
Frédéric Pétrot
,
2022/01/06
Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target
,
Alistair Francis
,
2022/01/09
[PATCH] target/riscv: Fix position of 'experimental' comment
,
Philipp Tomsich
,
2022/01/06
Re: [PATCH] target/riscv: Fix position of 'experimental' comment
,
Bin Meng
,
2022/01/06
Re: [PATCH] target/riscv: Fix position of 'experimental' comment
,
Philippe Mathieu-Daudé
,
2022/01/06
Re: [PATCH] target/riscv: Fix position of 'experimental' comment
,
Alistair Francis
,
2022/01/06
Re: [PATCH] target/riscv: Fix position of 'experimental' comment
,
Alistair Francis
,
2022/01/06
Re: [PATCH v7 00/18] Adding partial support for 128-bit riscv target
,
Alistair Francis
,
2022/01/06
Re: [PATCH v7 00/18] Adding partial support for 128-bit riscv target
,
Frédéric Pétrot
,
2022/01/06
Re: [PATCH v7 18/18] target/riscv: actual functions to realize crs 128-bit insns
,
Alistair Francis
,
2022/01/06
Re: [PATCH v4 2/3] target/riscv: Fixup setting GVA
,
Alistair Francis
,
2022/01/05
Re: [PATCH v4 2/3] target/riscv: Fixup setting GVA
,
Bin Meng
,
2022/01/06
Re: [PATCH v7 17/18] target/riscv: modification of the trans_csrxx for 128-bit support
,
Alistair Francis
,
2022/01/05
Re: [PATCH v7 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns
,
Alistair Francis
,
2022/01/05
Re: [PATCH v7 14/18] target/riscv: support for 128-bit M extension
,
Alistair Francis
,
2022/01/05
Re: [PATCH v7 13/18] target/riscv: support for 128-bit arithmetic instructions
,
Alistair Francis
,
2022/01/05
Re: [PATCH v3 12/12] target/riscv: Support virtual time context synchronization
,
Alistair Francis
,
2022/01/05
Re: [PATCH v3 11/12] target/riscv: Implement virtual time adjusting with vm state changing
,
Alistair Francis
,
2022/01/05
Re: [PATCH v3 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Alistair Francis
,
2022/01/05
RE: [PATCH v3 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Jiangyifei
,
2022/01/09
[PATCH v4 0/8] A collection of RISC-V cleanups and improvements
,
Alistair Francis
,
2022/01/05
[PATCH v4 4/8] hw/intc: sifive_plic: Cleanup remaining functions
,
Alistair Francis
,
2022/01/05
[PATCH v4 5/8] target/riscv: Mark the Hypervisor extension as non experimental
,
Alistair Francis
,
2022/01/05
[PATCH v4 1/8] hw/intc: sifive_plic: Add a reset function
,
Alistair Francis
,
2022/01/05
[PATCH v4 2/8] hw/intc: sifive_plic: Cleanup the write function
,
Alistair Francis
,
2022/01/05
[PATCH v4 7/8] hw/riscv: Use error_fatal for SoC realisation
,
Alistair Francis
,
2022/01/05
[PATCH v4 3/8] hw/intc: sifive_plic: Cleanup the read function
,
Alistair Francis
,
2022/01/05
[PATCH v4 6/8] target/riscv: Enable the Hypervisor extension by default
,
Alistair Francis
,
2022/01/05
[PATCH v4 8/8] hw/riscv: virt: Allow support for 32 cores
,
Alistair Francis
,
2022/01/05
Re: [PATCH v4 0/8] A collection of RISC-V cleanups and improvements
,
Alistair Francis
,
2022/01/05
Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
2022/01/05
Re: [PATCH v6 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
,
Alistair Francis
,
2022/01/05
Re: [PATCH v6 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
,
Frank Chang
,
2022/01/12
Re: [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu
,
Atish Patra
,
2022/01/05
Re: [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for
,
Atish Patra
,
2022/01/05
Re: [PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Frank Chang
,
2022/01/04
Re: [PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Anup Patel
,
2022/01/08
[RESEND PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
,
Bin Meng
,
2022/01/04
[RESEND PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
,
Bin Meng
,
2022/01/04
[RESEND PATCH v3 1/7] target/riscv: Add initial support for native debug
,
Bin Meng
,
2022/01/04
Re: [RESEND PATCH v3 1/7] target/riscv: Add initial support for native debug
,
Alistair Francis
,
2022/01/18
[RESEND PATCH v3 2/7] target/riscv: machine: Add debug state description
,
Bin Meng
,
2022/01/04
[RESEND PATCH v3 4/7] target/riscv: cpu: Add a config option for native debug
,
Bin Meng
,
2022/01/04
[RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write
,
Bin Meng
,
2022/01/04
Re: [RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write
,
Alistair Francis
,
2022/01/18
[RESEND PATCH v3 6/7] target/riscv: cpu: Enable native debug feature
,
Bin Meng
,
2022/01/04
[RESEND PATCH v3 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
,
Bin Meng
,
2022/01/04
[RESEND PATCH v3 3/7] target/riscv: debug: Implement debug related TCGCPUOps
,
Bin Meng
,
2022/01/04
[PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
,
Bin Meng
,
2022/01/04
[PATCH v3 2/7] target/riscv: machine: Add debug state description
,
Bin Meng
,
2022/01/04
[PATCH v3 4/7] target/riscv: cpu: Add a config option for native debug
,
Bin Meng
,
2022/01/04
[PATCH v3 3/7] target/riscv: debug: Implement debug related TCGCPUOps
,
Bin Meng
,
2022/01/04
[PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write
,
Bin Meng
,
2022/01/04
[PATCH v3 6/7] target/riscv: cpu: Enable native debug feature
,
Bin Meng
,
2022/01/04
[PATCH v3 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
,
Bin Meng
,
2022/01/04
[PATCH v3 1/7] target/riscv: Add initial support for native debug
,
Bin Meng
,
2022/01/04
[PATCH v2 0/3] Fix RVV calling incorrect RFV/RVD check functions bug
,
frank . chang
,
2022/01/04
[PATCH v2 1/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns
,
frank . chang
,
2022/01/04
Re: [PATCH v2 1/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns
,
Alistair Francis
,
2022/01/05
[PATCH v2 2/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns
,
frank . chang
,
2022/01/04
Re: [PATCH v2 2/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns
,
Alistair Francis
,
2022/01/05
[PATCH v2 3/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns
,
frank . chang
,
2022/01/04
Re: [PATCH v2 3/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns
,
Alistair Francis
,
2022/01/05
Re: [PATCH v2 0/3] Fix RVV calling incorrect RFV/RVD check functions bug
,
Alistair Francis
,
2022/01/05
[PATCH] roms/opensbi: Upgrade from v0.9 to v1.0
,
Bin Meng
,
2022/01/04
Re: [PATCH] roms/opensbi: Upgrade from v0.9 to v1.0
,
Alistair Francis
,
2022/01/05
Re: [PATCH] roms/opensbi: Upgrade from v0.9 to v1.0
,
Alistair Francis
,
2022/01/05
Re: [PATCH 1/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for widening fp insns
,
Alistair Francis
,
2022/01/04
[PATCH v2 0/2] Align SiFive PDMA behavior to real hardware
,
Jim Shu
,
2022/01/04
[PATCH v2 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
,
Jim Shu
,
2022/01/04
[PATCH v2 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
,
Jim Shu
,
2022/01/04
Re: [PATCH v2 0/2] Align SiFive PDMA behavior to real hardware
,
Alistair Francis
,
2022/01/04
Re: [PATCH 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Alistair Francis
,
2022/01/03
Re: [PATCH 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
,
Alistair Francis
,
2022/01/03
Re: [PATCH 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
,
Bin Meng
,
2022/01/03
Re: [PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
,
Alistair Francis
,
2022/01/03
Re: [PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
,
Bin Meng
,
2022/01/03
Re: [PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
,
Jim Shu
,
2022/01/04
Re: [PATCH v2 3/3] target/riscv: add support for svpbmt extension
,
Anup Patel
,
2022/01/01
Re: [PATCH v2 1/3] target/riscv: add support for svnapot extension
,
Anup Patel
,
2022/01/01
Re: [PATCH v2 2/3] target/riscv: add support for svinval extension
,
Anup Patel
,
2022/01/01
Re: [PATCH v2 2/3] target/riscv: add support for svinval extension
,
Weiwei Li
,
2022/01/02
Re: [PATCH v2 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
2022/01/01
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
2022/01/01
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
,
Richard Henderson
,
2022/01/01
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
2022/01/02
Re: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
2022/01/01
Re: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Richard Henderson
,
2022/01/01
Re: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
2022/01/02
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